公开(公告)号：US20060262240A1

公开(公告)日：2006-11-23

申请号：US11495634

申请日：2006-07-31

申请人： Kouichi Anno ,  Hitoshi Komeno ,  Tomonori Nishino

发明人： Kouichi Anno ,  Hitoshi Komeno ,  Tomonori Nishino

IPC分类号： G02F1/136 ,  G02F1/1335

CPC分类号： G02F1/133512 ,  G02F1/133371 ,  G02F2203/09

摘要： The present invention prevents a frame-like luminance difference generated in a portion which surrounds a light transmissive region. In a pixel region formed on a substrate, a first pixel electrode formed of a light transmissive conductive layer is formed in one light transmissive region which is formed by partitioning the pixel region and a second pixel electrode formed of a non-light transmissive conductive film is formed on the other light reflective region. The first pixel electrode is positioned as a lower layer with respect to an insulation film. A hole is formed in the insulation film in a region corresponding to the light transmissive region so as to expose the first pixel electrode. The second pixel electrode is formed on a light reflective region of the insulation film. Light shielding is performed at a portion corresponding to a side wall surface of the hole formed in the insulation film.

摘要翻译： 本发明防止在透光区域周围部分产生的帧状亮度差。 在形成在基板上的像素区域中，由透光导电层形成的第一像素电极形成在通过划分像素区域形成的一个透光区域中，并且由非透光性导电膜形成的第二像素电极为 形成在另一个光反射区域上。 第一像素电极被定位为相对于绝缘膜的下层。 在与透光区域对应的区域中的绝缘膜上形成孔，以露出第一像素电极。 第二像素电极形成在绝缘膜的光反射区域上。 在对应于形成在绝缘膜上的孔的侧壁表面的部分进行遮光。

公开(公告)号：US07342626B2

公开(公告)日：2008-03-11

申请号：US11495634

申请日：2006-07-31

申请人： Kouichi Anno ,  Hitoshi Komeno ,  Tomonori Nishino

发明人： Kouichi Anno ,  Hitoshi Komeno ,  Tomonori Nishino

IPC分类号： G02F1/136 ,  G02F1/1333

CPC分类号： G02F1/133512 ,  G02F1/133371 ,  G02F2203/09

摘要： The present invention prevents a frame-like luminance difference generated in a portion which surrounds a light transmissive region. In a pixel region formed on a substrate, a first pixel electrode formed of a light transmissive conductive layer is formed in one light transmissive region which is formed by partitioning the pixel region and a second pixel electrode formed of a non-light transmissive conductive film is formed on the other light reflective region. The first pixel electrode is positioned as a lower layer with respect to an insulation film. A hole is formed in the insulation film in a region corresponding to the light transmissive region so as to expose the first pixel electrode. The second pixel electrode is formed on a light reflective region of the insulation film. Light shielding is performed at a portion corresponding to a side wall surface of the hole formed in the insulation film.

摘要翻译： 本发明防止在透光区域周围部分产生的帧状亮度差。 在形成在基板上的像素区域中，由透光导电层形成的第一像素电极形成在通过划分像素区域形成的一个透光区域中，并且由非透光性导电膜形成的第二像素电极为 形成在另一个光反射区域上。 第一像素电极被定位为相对于绝缘膜的下层。 在与透光区域对应的区域中的绝缘膜上形成孔，以露出第一像素电极。 第二像素电极形成在绝缘膜的光反射区域上。 在对应于形成在绝缘膜上的孔的侧壁表面的部分进行遮光。

公开(公告)号：US20060152642A1

公开(公告)日：2006-07-13

申请号：US11375126

申请日：2006-03-15

申请人： Hitoshi Komeno ,  Kouichi Anno

发明人： Hitoshi Komeno ,  Kouichi Anno

IPC分类号： G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F1/136213 ,  G02F2001/13456

摘要： Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.

摘要翻译： 即使在左右相框区域上拉拽栅极线的情况下，也可以防止由栅极线和栅极线绕入线构成的栅极布线图案和由存储器构成的存储配线图案 线路和一条共同的线路，将存储线路彼此相互连接。 栅极线GL 1，GL 2被左右图像帧区域中的栅极线绕线GLL 1，GLL 2拉动。 在左右相框区域上形成有连接存储线STL的公共线B 2，B 3。 此外，由栅极线GL1，GL2和栅极线绕线GLL 1，GLL 2构成的栅极布线图案和由存储线STL和公共线B构成的存储布线图案 2，B 3不要交叉。

公开(公告)号：US20050225709A1

公开(公告)日：2005-10-13

申请号：US11148165

申请日：2005-06-09

申请人： Hitoshi Komeno ,  Kouichi Anno

发明人： Hitoshi Komeno ,  Kouichi Anno

IPC分类号： G02F1/133 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F1/136213 ,  G02F2001/13456

摘要： Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.

摘要翻译： 即使在左右相框区域上拉拽栅极线的情况下，也可以防止由栅极线和栅极线绕入线构成的栅极布线图案和由存储器构成的存储配线图案 线路和一条共同的线路，将存储线路彼此相互连接。 栅极线GL 1，GL 2被左右图像帧区域中的栅极线绕线GLL 1，GLL 2拉动。 在左右相框区域上形成有连接存储线STL的公共线B 2，B 3。 此外，由栅极线GL1，GL2和栅极线绕线GLL 1，GLL 2构成的栅极布线图案和由存储线STL和公共线B构成的存储布线图案 2，B 3不要交叉。

公开(公告)号：US07471349B2

公开(公告)日：2008-12-30

申请号：US11375126

申请日：2006-03-15

申请人： Hitoshi Komeno ,  Kouichi Anno

发明人： Hitoshi Komeno ,  Kouichi Anno

IPC分类号： G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F1/136213 ,  G02F2001/13456

摘要： Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.

摘要翻译： 即使在左右相框区域上拉拽栅极线的情况下，也可以防止由栅极线和栅极线绕入线构成的栅极布线图案和由存储器构成的存储配线图案 线路和一条共同的线路，将存储线路彼此相互连接。 栅极线GL1，GL2被左右图像帧区域中的栅极线绕线GLL1，GLL2拉动。 将存储线STL彼此连接的公共线B2，B3形成在左右相框区域。 此外，由栅极线GL1，GL2和栅极线绕线GLL1，GLL2构成的栅极布线图案和由存储线STL和公共线B2，B3构成的存储布线图案不是 互相交叉

公开(公告)号：US20050231678A1

公开(公告)日：2005-10-20

申请号：US11154566

申请日：2005-06-17

申请人： Hitoshi Komeno ,  Kouichi Anno

发明人： Hitoshi Komeno ,  Kouichi Anno

IPC分类号： G02F1/133 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F1/136213 ,  G02F2001/13456

摘要： Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.

公开(公告)号：US07821584B2

公开(公告)日：2010-10-26

申请号：US12292331

申请日：2008-11-17

申请人： Hitoshi Komeno ,  Kouichi Anno

发明人： Hitoshi Komeno ,  Kouichi Anno

IPC分类号： G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F1/136213 ,  G02F2001/13456

摘要： Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.

摘要翻译： 即使在左右相框区域上拉拽栅极线的情况下，也可以防止由栅极线和栅极线绕入线构成的栅极布线图案和由存储器构成的存储配线图案 线路和一条共同的线路，将存储线路彼此相互连接。 栅极线GL1，GL2被左右图像帧区域中的栅极线绕线GLL1，GLL2拉动。 将存储线STL彼此连接的公共线B2，B3形成在左右相框区域。 此外，由栅极线GL1，GL2和栅极线绕线GLL1，GLL2构成的栅极布线图案和由存储线STL和公共线B2，B3构成的存储布线图案不是 互相交叉

公开(公告)号：US06710839B2

公开(公告)日：2004-03-23

申请号：US10235890

申请日：2002-09-06

申请人： Hitoshi Komeno ,  Kouichi Anno

发明人： Hitoshi Komeno ,  Kouichi Anno

IPC分类号： G02F11345

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F1/136213 ,  G02F2001/13456

摘要： Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.

摘要翻译： 即使在左右相框区域上拉拽栅极线的情况下，也可以防止由栅极线和栅极线绕入线构成的栅极布线图案和由存储器构成的存储配线图案 线路和一条共同的线路，将存储线路彼此相互连接。 栅极线GL1，GL2被左右图像帧区域中的栅极线绕线GLL1，GLL2拉动。 将存储线STL彼此连接的公共线B2，B3形成在左右相框区域。 此外，由栅极线GL1，GL2和栅极线绕线GLL1，GLL2构成的栅极布线图案和由存储线STL和公共线B2，B3构成的存储布线图案不是 互相交叉

公开(公告)号：US20090079889A1

公开(公告)日：2009-03-26

申请号：US12292331

申请日：2008-11-17

申请人： Hitoshi Komeno ,  Kouichi Anno

发明人： Hitoshi Komeno ,  Kouichi Anno

IPC分类号： G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F1/136213 ,  G02F2001/13456

摘要： Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.

摘要翻译： 即使在左右相框区域上拉拽栅极线的情况下，也可以防止由栅极线和栅极线绕入线构成的栅极布线图案和由存储器构成的存储配线图案 线路和一条共同的线路，将存储线路彼此相互连接。 栅极线GL1，GL2被左右图像帧区域中的栅极线绕线GLL1，GLL2拉动。 将存储线STL彼此连接的公共线B2，B3形成在左右相框区域。 此外，由栅极线GL1，GL2和栅极线绕线GLL1，GLL2构成的栅极布线图案和由存储线STL和公共线B2，B3构成的存储布线图案不是 互相交叉

公开(公告)号：US07164453B2

公开(公告)日：2007-01-16

申请号：US11154566

申请日：2005-06-17

申请人： Hitoshi Komeno ,  Kouichi Anno

发明人： Hitoshi Komeno ,  Kouichi Anno

IPC分类号： G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F1/136213 ,  G02F2001/13456

摘要： Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.

摘要翻译： 即使在左右相框区域上拉拽栅极线的情况下，也可以防止由栅极线和栅极线绕入线构成的栅极布线图案和由存储器构成的存储配线图案 线路和一条共同的线路，将存储线路彼此相互连接。 栅极线GL 1，GL 2被左右图像帧区域中的栅极线绕线GLL 1，GLL 2拉动。 在左右相框区域上形成有连接存储线STL的公共线B 2，B 3。 此外，由栅极线GL1，GL2和栅极线绕线GLL 1，GLL 2构成的栅极布线图案和由存储线STL和公共线B构成的存储布线图案 2，B 3不要交叉。