公开(公告)号：US4802168A

公开(公告)日：1989-01-31

申请号：US11175

申请日：1987-02-05

申请人： Koyu Yamanoi ,  Yoshio Yoshizakiya ,  Masayoshi Dehara

发明人： Koyu Yamanoi ,  Yoshio Yoshizakiya ,  Masayoshi Dehara

IPC分类号： G01R31/319 ,  G06F3/04

CPC分类号： G01R31/3191 ,  G01R31/31928

摘要： A test signal generating circuit for generating a test signal for testing logic circuits comprises four delay units each including a setting circuitry for setting a delay time, a gate and a counter for counting clock pulses in number corresponding to the delay time placed in the setting circuitry. The output signals of two delay units are applied to a flip-flop as set input signals, while the output signals of the other two delay units are applied to the flip-flop as reset input signals, whereby the timing and/or waveform of the test signal outputted by the flip-flop is varied in dependence on the values placed in the setting circuitries.

摘要翻译： 用于产生用于测试逻辑电路的测试信号的测试信号产生电路包括四个延迟单元，每个延迟单元包括用于设置延迟时间的设置电路，用于计数对应于设置电路中的延迟时间的数量的时钟脉冲的门和计数器 。 两个延迟单元的输出信号作为设置的输入信号施加到触发器，而另外两个延迟单元的输出信号作为复位输入信号施加到触发器，由此，定时和/或波形 触发器输出的测试信号根据设置电路中的值而变化。

公开(公告)号：US4758738A

公开(公告)日：1988-07-19

申请号：US45098

申请日：1987-05-01

申请人： Koyu Yamanoi ,  Yoshio Yoshizakiya

发明人： Koyu Yamanoi ,  Yoshio Yoshizakiya

IPC分类号： G01R31/28 ,  H03K5/135 ,  H03K5/13

CPC分类号： H03K5/135

摘要： A timing signal generating apparatus comprises a first shift register having an input supplied with a first select signal and shifting the first select signal with a first reference clock signal, a second shift register having an input supplied with timing data for shifting the timing data with the first reference clock signal, a first selector having an input supplied with the output of the first shift register and extracting the output from the first shift register at a position corresponding to the stage designated by a second select signal, a second selector having an input supplied with the output of the second shift register for producing the output from the second shift register at a position corresponding to the stage designated by the second select signal, a gate circuit having inputs supplied with a second reference clock signal delayed in phase relative to the first reference clock and the output of the first selector, respectively, a counter for counting a clock signal of a repetition period shorter than that of the first reference clock signal, the counter being reset in response to the output of the gate circuit, a setting circuit having an address input supplied with the output of the second selector, an inhibit signal generating circuit having an input supplied with the second select signal, and a coincidence detection circuit having inputs supplied with the output of the counter, the output of the inhibit signal generating circuit and the output of the setting circuit, respectively. The coincidence detection circuit responds to the output of the inhibit signal generating circuit to be inhibited from producing the output for the period during which the second select signal is changed over. The timing signal derived from the coincidence detection circuit is delayed for a time equal to a sum resulting from the addition of the period of the reference clock signal multiplied with the stage number of the shift registers and a value set at the setting circuit.