公开(公告)号：US06640262B1

公开(公告)日：2003-10-28

申请号：US09467724

申请日：1999-12-20

申请人： Krishna Uppunda ,  Eric R. Davis ,  Nathaniel Henderson ,  Chi-Lie Wang ,  Alexander Herrera

发明人： Krishna Uppunda ,  Eric R. Davis ,  Nathaniel Henderson ,  Chi-Lie Wang ,  Alexander Herrera

IPC分类号： G06F15177

CPC分类号： G06F15/7867

摘要： A method and apparatus for automatically configuring a configurable integrated circuit. One embodiment comprises a method for automatically loading data including configuration data to a configurable integrated circuit upon initialization of a system in which the configurable integrated circuit is embedded. The method of one embodiment comprises storing a plurality of commands and a plurality of data elements in a non-volatile memory of the system. The method further comprises reading contents of an initial address in the non-volatile memory. If the initial address contains a command, depending upon a type of the command, the method comprises writing contents of a next address in the non-volatile memory to a register space of the configurable integrated circuit, to a configuration space of the configurable integrated circuit, or to a command space of the configurable integrated circuit.

摘要翻译： 一种用于自动配置可配置集成电路的方法和装置。 一个实施例包括在嵌入可配置集成电路的系统的初始化时自动将包括配置数据的数据加载到可配置集成电路的方法。 一个实施例的方法包括将多个命令和多个数据元素存储在系统的非易失性存储器中。 该方法还包括读取非易失性存储器中的初始地址的内容。 如果初始地址包含命令，则取决于命令的类型，该方法包括将非易失性存储器中的下一个地址的内容写入可配置集成电路的寄存器空间到可配置集成电路的配置空间 ，或可配置集成电路的命令空间。

公开(公告)号：US06678728B1

公开(公告)日：2004-01-13

申请号：US09454783

申请日：1999-12-03

申请人： Krishna Uppunda ,  Eric Davis ,  Nathaniel Henderson ,  Chi-Lie Wang ,  Alexander Herrera

发明人： Krishna Uppunda ,  Eric Davis ,  Nathaniel Henderson ,  Chi-Lie Wang ,  Alexander Herrera

IPC分类号： G06F15177

CPC分类号： H04L12/12 ,  Y02D50/40

摘要： A method and apparatus for automatically loading device status information into a network device. One embodiment comprises an apparatus in a network device, wherein the network device enters a sleep state under particular conditions. In one embodiment, the apparatus is for communicating with other devices on the network and comprises control circuitry that controls communication between the network device and the other devices on the network. The apparatus further comprises a memory device that stores configuration data for the control circuitry, wherein at least a portion of the configuration data is loaded into the control circuitry upon initialization of the network device. The apparatus further comprises a buffer that stores keep-alive data that is transmitted to a plurality of the other devices in the network to refresh the presence of the network device in the network, wherein the keep-alive data is loaded into the buffer from the memory device upon initialization of the network device.

摘要翻译： 一种用于将设备状态信息自动加载到网络设备中的方法和装置。 一个实施例包括网络设备中的设备，其中网络设备在特定条件下进入睡眠状态。 在一个实施例中，该设备用于与网络上的其他设备进行通信，并且包括控制网络设备与网络上的其他设备之间的通信的控制电路。 该装置还包括存储器件，其存储用于控制电路的配置数据，其中当网络设备初始化时，配置数据的至少一部分被加载到控制电路中。 所述设备还包括缓冲器，其存储传送到网络中的多个其他设备的保持活动数据，以刷新网络中网络设备的存在，其中保持活动数据从 初始化网络设备时的存储设备。

公开(公告)号：US06556580B1

公开(公告)日：2003-04-29

申请号：US09465984

申请日：1999-12-16

申请人： Chi-Lie Wang ,  Lai-Chin Lo ,  Ngo Thanh Ho ,  Krishna Uppunda

发明人： Chi-Lie Wang ,  Lai-Chin Lo ,  Ngo Thanh Ho ,  Krishna Uppunda

IPC分类号： H04L1256

CPC分类号： H04L49/9063 ,  H04L12/12 ,  H04L47/50 ,  Y02D50/40

摘要： A transmit packet buffer (TPB) is used on a network interface card (NIC) to store downloaded packets and forward them through the media access controller (MAC) and the physical layer interface (PHY) onto the wire. A multi-function TPB is implemented to allow the multiple usage of this buffer. Packets may be downloaded to this buffer through multiple sources. Different types of the packets may each be stored at predefined locations. For example, while the second half of the TPB is used to transmit keep-alive or alert-on-LAN packets, the first half may be used to compare received packets with a wake-up pattern for system wake-up. With multi-function support, various PC management functions may be implemented more effectively and with reduced cost.

摘要翻译： 在网络接口卡（NIC）上使用发送分组缓冲器（TPB）来存储下载的分组，并将它们通过媒体接入控制器（MAC）和物理层接口（PHY）转发到线路上。 实现多功能TPB以允许该缓冲器的多次使用。 数据包可以通过多个源下载到此缓冲区。 不同类型的分组可以各自存储在预定义的位置。 例如，当TPB的后半部分用于传送保持活动或LAN报警时，上半部分可以用于将接收的分组与用于系统唤醒的唤醒模式进行比较。 通过多功能支持，可以更有效地实现各种PC管理功能，降低成本。

公开(公告)号：US06360278B1

公开(公告)日：2002-03-19

申请号：US09321307

申请日：1999-05-27

申请人： Burton B. Lo ,  Krishna Uppunda ,  Anthony L. Pan

发明人： Burton B. Lo ,  Krishna Uppunda ,  Anthony L. Pan

IPC分类号： G06F1300

CPC分类号： G06F13/385

摘要： A first-in-first-out (FIFO) entry point circuit for a network interface card. The novel circuit of the present invention provides a FIFO entry point circuit within a network interface card (NIC). The FIFO implementation allows multiple downlist pointers to be maintained within the transmit (Tx) FIFO entry point circuit and also allows multiple uplist pointers to be maintained for the receive (Rx) FIFO entry point circuit. For the Tx FIFO entry point circuit, only one register is visible to the processor which can load a memory pointer into the entry point thereby placing the memory pointer on the bottom on the FIFO. Only one register is seen for the Rx FIFO entry point circuit. With respect to the Tx FIFO entry point circuit, the NIC takes the oldest entry, obtains the packet from memory that is indicated by the corresponding pointer and transmits the packet onto a network. If the packet points to a next packet, then that next packet is sent, otherwise the next pointer of the Tx FIFO entry point is then processed by the NIC. Signals indicate when the Rx or Tx FIFO entry points are full. An analogous process operates for the Rx FIFO entry point. Providing a queued entry point reduces processor utilization and PCI bus utilization in communicating packets with the network because memory pointers can be directly pushed onto the transmit FIFO by the processor without encountering race conditions. Providing a queued entry point also increases NIC efficiency by avoiding processor initiated NIC stalls. Both improve quality of service performance.

摘要翻译： 用于网络接口卡的先进先出（FIFO）入口点电路。 本发明的新颖电路提供了网络接口卡（NIC）内的FIFO入口点电路。 FIFO实现允许在发送（Tx）FIFO入口点电路内保持多个下行指针，并且还允许为接收（Rx）FIFO入口点电路维护多个上行指针。 对于Tx FIFO入口点电路，处理器只能看到一个寄存器，可以将存储器指针加载到入口点，从而将存储器指针放在FIFO的底部。 Rx FIFO入口点电路只能看到一个寄存器。 对于Tx FIFO入口点电路，NIC采取最早的条目，从由相应指针指示的存储器获得分组，并将该分组发送到网络上。 如果分组指向下一个分组，则发送下一个分组，否则Tx FIFO入口点的下一个指针然后由NIC处理。 信号指示Rx或Tx FIFO入口点何时已满。 对于Rx FIFO入口点进行类似的处理。 提供排队的入口点降低了与网络通信数据包的处理器利用率和PCI总线利用率，因为存储器指针可以被处理器直接推送到发送FIFO，而不会遇到竞争条件。 提供排队的入口点还可以通过避免处理器启动的网卡停顿来提高网卡的效率。 两者都提高了服务质量的表现。

公开(公告)号：US06667983B1

公开(公告)日：2003-12-23

申请号：US09321068

申请日：1999-05-27

申请人： Burton B. Lo ,  Krishna Uppunda ,  Anthony L. Pan

发明人： Burton B. Lo ,  Krishna Uppunda ,  Anthony L. Pan

IPC分类号： H04L1228

CPC分类号： H04L47/24 ,  H04L49/90

摘要： A scaleable priority arbiter for arbitrating between multiple FIFO entry points of a network interface card (NIC). The circuit provides a separate FIFO entry point circuit within the NIC for each data packet priority type. Exemplary priority types, from highest to lowest, include isochronous, priority 1, priority 2, . . . , priority n. A separate set of FIFO entry points are provided for NIC transmitting (Tx) and for NIC receiving (Rx). For each of the Tx FIFO entry points, a single Tx entry point register is seen by the processor and multiple downlist pointers are also maintained. The Tx entry point registers all feed a scaleable priority arbiter which selects the next message for transmission. The scaleable priority arbiter is made of scaleable circuit units that contain a sequential element controlling a multiplexer. The multiplexer selects between two inputs, a first input is dedicated to data packets of the priority type corresponding to the circuit stage and the other input comes from the lower priority chain. In one embodiment, timers regulate the transmission of isochronous packets. The arbiter transmits the isochronous packet, if any, with the timer and otherwise allows the next stage a transmit turn. The next stage checks if a priority 1 packet is present and if a priority 1 packet was not sent the last time its turn was reached. If yes, the priority 1 packet is sent, if not, then the above decision is repeated with respect to the next lower priority circuit stage. Priority arbitration improves quality of service performance.

摘要翻译： 用于在网络接口卡（NIC）的多个FIFO入口点之间进行仲裁的可扩展优先仲裁器。 该电路为每个数据包优先级类型的NIC提供单独的FIFO入口点电路。 从最高到最低的优先级类型包括等时，优先级1，优先级2。 。 。 ，优先级n。 提供了一组单独的FIFO入口点，用于NIC传输（Tx）和NIC接收（Rx）。 对于每个Tx FIFO入口点，处理器看到单个Tx入口点寄存器，并且还保留了多个下划线指针。 Tx入口点注册所有馈送可扩展优先仲裁器，其选择下一个消息进行传输。 可扩展优先仲裁器由包含控制复用器的顺序元件的可缩放电路单元组成。 多路复用器在两个输入之间进行选择，第一个输入专用于与电路级对应的优先级类型的数据包，另一个输入来自较低优先级的链。 在一个实施例中，定时器调节同步分组的传输。 仲裁器用定时器发送等时数据包（如果有的话），否则允许下一级传输转。 下一个阶段检查是否存在优先级1数据包，并且在最后一次到达时没有发送优先级1数据包。 如果是，则发送优先级1分组，否则，则针对下一个较低优先级的电路级重复上述决定。 优先仲裁提高了服务质量。