公开(公告)号：US06360278B1

公开(公告)日：2002-03-19

申请号：US09321307

申请日：1999-05-27

申请人： Burton B. Lo ,  Krishna Uppunda ,  Anthony L. Pan

发明人： Burton B. Lo ,  Krishna Uppunda ,  Anthony L. Pan

IPC分类号： G06F1300

CPC分类号： G06F13/385

摘要： A first-in-first-out (FIFO) entry point circuit for a network interface card. The novel circuit of the present invention provides a FIFO entry point circuit within a network interface card (NIC). The FIFO implementation allows multiple downlist pointers to be maintained within the transmit (Tx) FIFO entry point circuit and also allows multiple uplist pointers to be maintained for the receive (Rx) FIFO entry point circuit. For the Tx FIFO entry point circuit, only one register is visible to the processor which can load a memory pointer into the entry point thereby placing the memory pointer on the bottom on the FIFO. Only one register is seen for the Rx FIFO entry point circuit. With respect to the Tx FIFO entry point circuit, the NIC takes the oldest entry, obtains the packet from memory that is indicated by the corresponding pointer and transmits the packet onto a network. If the packet points to a next packet, then that next packet is sent, otherwise the next pointer of the Tx FIFO entry point is then processed by the NIC. Signals indicate when the Rx or Tx FIFO entry points are full. An analogous process operates for the Rx FIFO entry point. Providing a queued entry point reduces processor utilization and PCI bus utilization in communicating packets with the network because memory pointers can be directly pushed onto the transmit FIFO by the processor without encountering race conditions. Providing a queued entry point also increases NIC efficiency by avoiding processor initiated NIC stalls. Both improve quality of service performance.

摘要翻译： 用于网络接口卡的先进先出（FIFO）入口点电路。 本发明的新颖电路提供了网络接口卡（NIC）内的FIFO入口点电路。 FIFO实现允许在发送（Tx）FIFO入口点电路内保持多个下行指针，并且还允许为接收（Rx）FIFO入口点电路维护多个上行指针。 对于Tx FIFO入口点电路，处理器只能看到一个寄存器，可以将存储器指针加载到入口点，从而将存储器指针放在FIFO的底部。 Rx FIFO入口点电路只能看到一个寄存器。 对于Tx FIFO入口点电路，NIC采取最早的条目，从由相应指针指示的存储器获得分组，并将该分组发送到网络上。 如果分组指向下一个分组，则发送下一个分组，否则Tx FIFO入口点的下一个指针然后由NIC处理。 信号指示Rx或Tx FIFO入口点何时已满。 对于Rx FIFO入口点进行类似的处理。 提供排队的入口点降低了与网络通信数据包的处理器利用率和PCI总线利用率，因为存储器指针可以被处理器直接推送到发送FIFO，而不会遇到竞争条件。 提供排队的入口点还可以通过避免处理器启动的网卡停顿来提高网卡的效率。 两者都提高了服务质量的表现。

公开(公告)号：US6055594A

公开(公告)日：2000-04-25

申请号：US139148

申请日：1998-08-24

申请人： Burton B. Lo ,  Anthony L. Pan

发明人： Burton B. Lo ,  Anthony L. Pan

IPC分类号： G06F13/16 ,  G06F13/00

CPC分类号： G06F13/1678

摘要： A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for performing word length reads and writes to an external memory module containing a plurality of integrated circuit (IC) memory chips. The interface circuit contains a respective multiplexer and a respective register circuit for each byte of the word length data. The multiplexers select a byte of data from either an on-chip data bus or from a bus carrying data read from the external memory module. To perform a full length word write, the data from the on-chip bus is loaded into the registers (via the multiplexers) and then written to the memory module. To perform a partial length word write, a pre-read operation is performed at the target address and a word length data is loaded into the registers. The new data is then received over the on-chip data bus and routed by the multiplexers into the byte locations to be changed. The properly merged data is then written as a full length word to the memory module. To perform a full length word read, a word of data is loaded into the byte registers and then forwarded over the on-chip data bus. By the provision of a pre-read operation, all of the IC memory chips can share the same chip enable, output enable and write enable control signals thereby reducing pin count on the integrated circuit that contains the interface circuit.

摘要翻译： 一个字节可访问存储器接口电路，使用一组减少的存储器控​​制信号。 本发明包括具有减少的一组存储器控制信号的接口电路，用于对包含多个集成电路（IC）存储器芯片的外部存储器模块执行字长读取和写入。 接口电路包含相应的多路复用器和用于字长数据的每个字节的相应寄存器电路。 多路复用器从片上数据总线或从承载从外部存储器模块读取的数据的总线选择一个字节的数据。 要执行全长字写入，片上总线的数据将通过多路复用器加载到寄存器中，然后写入存储器模块。 为了执行部分长度字写入，在目标地址处执行预读操作，并将字长数据加载到寄存器中。 然后通过片上数据总线接收新数据，并由多路复用器路由到要更改的字节位置。 然后将适当合并的数据作为全长字写入内存模块。 要执行全长字读取，数据字被加载到字节寄存器中，然后通过片上数据总线转发。 通过提供预读操作，所有IC存储器芯片可以共享相同的芯片使能，输出使能和写使能控制信号，从而减少包含接口电路的集成电路的引脚数。

公开(公告)号：US06667983B1

公开(公告)日：2003-12-23

申请号：US09321068

申请日：1999-05-27

申请人： Burton B. Lo ,  Krishna Uppunda ,  Anthony L. Pan

发明人： Burton B. Lo ,  Krishna Uppunda ,  Anthony L. Pan

IPC分类号： H04L1228

CPC分类号： H04L47/24 ,  H04L49/90

摘要： A scaleable priority arbiter for arbitrating between multiple FIFO entry points of a network interface card (NIC). The circuit provides a separate FIFO entry point circuit within the NIC for each data packet priority type. Exemplary priority types, from highest to lowest, include isochronous, priority 1, priority 2, . . . , priority n. A separate set of FIFO entry points are provided for NIC transmitting (Tx) and for NIC receiving (Rx). For each of the Tx FIFO entry points, a single Tx entry point register is seen by the processor and multiple downlist pointers are also maintained. The Tx entry point registers all feed a scaleable priority arbiter which selects the next message for transmission. The scaleable priority arbiter is made of scaleable circuit units that contain a sequential element controlling a multiplexer. The multiplexer selects between two inputs, a first input is dedicated to data packets of the priority type corresponding to the circuit stage and the other input comes from the lower priority chain. In one embodiment, timers regulate the transmission of isochronous packets. The arbiter transmits the isochronous packet, if any, with the timer and otherwise allows the next stage a transmit turn. The next stage checks if a priority 1 packet is present and if a priority 1 packet was not sent the last time its turn was reached. If yes, the priority 1 packet is sent, if not, then the above decision is repeated with respect to the next lower priority circuit stage. Priority arbitration improves quality of service performance.

摘要翻译： 用于在网络接口卡（NIC）的多个FIFO入口点之间进行仲裁的可扩展优先仲裁器。 该电路为每个数据包优先级类型的NIC提供单独的FIFO入口点电路。 从最高到最低的优先级类型包括等时，优先级1，优先级2。 。 。 ，优先级n。 提供了一组单独的FIFO入口点，用于NIC传输（Tx）和NIC接收（Rx）。 对于每个Tx FIFO入口点，处理器看到单个Tx入口点寄存器，并且还保留了多个下划线指针。 Tx入口点注册所有馈送可扩展优先仲裁器，其选择下一个消息进行传输。 可扩展优先仲裁器由包含控制复用器的顺序元件的可缩放电路单元组成。 多路复用器在两个输入之间进行选择，第一个输入专用于与电路级对应的优先级类型的数据包，另一个输入来自较低优先级的链。 在一个实施例中，定时器调节同步分组的传输。 仲裁器用定时器发送等时数据包（如果有的话），否则允许下一级传输转。 下一个阶段检查是否存在优先级1数据包，并且在最后一次到达时没有发送优先级1数据包。 如果是，则发送优先级1分组，否则，则针对下一个较低优先级的电路级重复上述决定。 优先仲裁提高了服务质量。

公开(公告)号：US06366973B1

公开(公告)日：2002-04-02

申请号：US09304034

申请日：1999-05-03

申请人： Burton B. Lo ,  Anthony L. Pan

发明人： Burton B. Lo ,  Anthony L. Pan

IPC分类号： G06F1340

CPC分类号： G06F13/4059

摘要： A slave interface circuit for providing communication between a PCI (Peripheral Component Interconnect) bus domain and an ASB (Advanced System Bus) bus domain. The novel circuit is an integrated interface for communicating using the AMBA (Advanced Microcontroller Bus Architecture) ASB protocol and translating ASB commands into PCI like commands. Embodiments include interfaces that are particularly suited for FPGA (field programmable gate array) and ASIC (application specific integrated circuit) implementations. A high-speed embodiment is also discussed allowing prefetch functionality. Input latches catch ASB commands on the falling edge of the ASB clock and then circuits reformat the data using size information and address bits from the ASB bus. This allows byte, halfword and word accesses. Byte readback data are provided on all four byte lanes and halfword readback data are provided on both halfword lanes. The reformatted data is latched into a set of request registers on the next rising edge of the ASB clock. During an ASB read request, the read data is latched on the rising edge of the ASB clock such that the ASB master agent can latch its requested data on the next falling edge of the ASB clock. The other handshake signals are latched on the falling edge of the ASB clock. An ASB master agent can sense the handshake on the rising edge of the ASB clock. Pipeline architecture allows the bus protocols to operate at optimum speed and supports the natural flow of data between the ASB and PCI domains without the need for wait cycles. Pipelined ASB burst cycles are supported.

摘要翻译： 用于在PCI（外围组件互连）总线域和ASB（高级系统总线）总线域之间提供通信的从接口电路。 新颖的电路是用于使用AMBA（高级微控制器总线架构）ASB协议进行通信并将ASB命令转换为PCI的命令的集成接口。 实施例包括特别适用于FPGA（现场可编程门阵列）和ASIC（专用集成电路）实现的接口。 还讨论了允许预取功能的高速实施例。 输入锁存器在ASB时钟的下降沿捕获ASB命令，然后使用ASB总线的大小信息和地址位重新格式化数据。 这允许字节，半字和字访问。 所有四字节通道都提供字节回读数据，半字通道上提供半字回读数据。 重新格式化的数据在ASB时钟的下一个上升沿被锁存到一组请求寄存器中。 在ASB读取请求期间，读取数据在ASB时钟的上升沿被锁存，使得ASB主代理可以在ASB时钟的下一个下降沿锁存其请求的数据。 另一个握手信号在ASB时钟的下降沿锁存。 ASB主代理可以在ASB时钟的上升沿感知握手。 管道架构允许总线协议以最佳速度运行，并支持ASB和PCI域之间的数据自然流动，而无需等待周期。 支持流水线ASB突发周期。

公开(公告)号：US06341135B1

公开(公告)日：2002-01-22

申请号：US09032382

申请日：1998-02-26

申请人： Marwan A. Fawal ,  Burton B. Lo ,  Anthony L. Pan

发明人： Marwan A. Fawal ,  Burton B. Lo ,  Anthony L. Pan

IPC分类号： G01R1900

CPC分类号： H04L25/0266 ,  H04L12/40032 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0286 ,  H04L25/0292

摘要： NMOS transistor buffers are used to buffer the output of a system. The system can include a network interface card. The NMOS transistor buffers receive the output of the shaped Ethernet data signals and drive a transformer. The NMOS transistor buffers allow for low power consumption while a feedback monitoring system provides stability by controlling the inputs to the NMOS transistors.

摘要翻译： NMOS晶体管缓冲器用于缓冲系统的输出。 该系统可以包括一个网络接口卡。 NMOS晶体管缓冲器接收成形以太网数据信号的输出并驱动变压器。 NMOS晶体管缓冲器允许低功耗，而反馈监控系统通过控制对NMOS晶体管的输入来提供稳定性。

公开(公告)号：US06247082B1

公开(公告)日：2001-06-12

申请号：US09186209

申请日：1998-11-03

申请人： Burton B. Lo ,  Anthony L. Pan

发明人： Burton B. Lo ,  Anthony L. Pan

IPC分类号： G06F100

CPC分类号： G06F13/405

摘要： A method and circuit for handshaking information across multiple clock domains within an electronic system. The environment of the present invention includes an electronic or computerized system having at least two subsystem domains (a first domain and a second domain) operating at different clock rates (a first clock and a second clock). The present invention includes a handshake circuit coupled between the first and second domains for providing the required handshaking signals to control the transfer of data between the first domain (master) and the second domain (slave). An information bus is coupled between the domains. The handshake circuit is such that double synchronization is not required and the design of the present invention is dynamic such that it is operable between clock domains of varying frequency. The present invention utilizes the asynchronous input of a flip-flop circuit to catch the pertinent handshaking signals between clock domains. The D input and the clock input of the flip-flop circuit are coupled to the master clock domain and the master clock domain receives a ready signal back. When ready is asserted, the master domain may assert a request (from the master domain) over the D input and hold data. The Q output is coupled to a request (to the slave domain) which is also coupled as an input to a NOR circuit. An acknowledge signal is coupled to the asynchronous flip-flip input as a clear and also coupled to the second input of the NOR circuit. The output of the NOR circuit generates the ready signal.

摘要翻译： 一种用于在电子系统内的多个时钟域握手信息的方法和电路。 本发明的环境包括具有以不同时钟速率（第一时钟和第二时钟）操作的至少两个子系统域（第一域和第二域）的电子或计算机化系统。 本发明包括一个耦合在第一和第二域之间的握手电路，用于提供所需的握手信号以控制第一域（主设备）与第二域（从设备）之间的数据传输。 信息总线耦合在域之间。 握手电路使得不需要双重同步，并且本发明的设计是动态的，使得其可在可变频率的时钟域之间操作。 本发明利用触发器电路的异步输入来捕捉时钟域之间的相关握手信号。 触发器电路的D输入和时钟输入耦合到主时钟域，并且主时钟域接收就绪信号。 当准备就绪时，主域可以通过D输入和保持数据来断言来自主域的请求。 Q输出耦合到一个请求（到从属域），该请求也作为输入耦合到NOR电路。 确认信号作为清零耦合到异步翻盖输入，并且还耦合到NOR电路的第二输入端。 NOR电路的输出产生就绪信号。

公开(公告)号：US06185607B2

公开(公告)日：2001-02-06

申请号：US09085395

申请日：1998-05-26

申请人： Burton B. Lo ,  Anthony L. Pan ,  Pauline Cheng

发明人： Burton B. Lo ,  Anthony L. Pan ,  Pauline Cheng

IPC分类号： G06F15167

CPC分类号： H04L29/06 ,  H04L69/08

摘要： A method for managing data transfers with minimal host processor involvement. Data is transferred between a peripheral device coupled to a host computer and a network device over a high performance bus. In one exemplary embodiment, data is transferred over a bus utilizing the IEEE 1394 communication protocol and a network utilizing the Ethernet communication protocol. The novel data transfer method advantageously minimizes the involvement of the host computer's processor in the management of data transfers, thus maximizing the host processor's availability for performing other computations. Specifically, to transfer data from the peripheral device to the network, the host processor generates a data pointer table and sends it to the network device. A processor in the network device then takes over data transfer management, using information in the data pointer table to locate and transmit the designated block of data from the peripheral device to the network. In another embodiment, the present invention determines whether the size of a data block to be transferred exceeds the maximum packet size for the relevant communication protocol used by the bus or the network. If such a limit exists and is exceeded, the data pending transfer is divided into multiple packets, such that each packet conforms to the maximum packet size of the limiting protocol. Then, the smaller packets are transmitted iteratively until the entire data block is transferred. As such, the present invention eliminates the incompatibility problem posed by the differences in packet sizes among different communication protocols.

摘要翻译： 用于以最少的主机处理器参与来管理数据传输的方法。 数据通过高性能总线在耦合到主计算机的外围设备和网络设备之间传送。 在一个示例性实施例中，使用IEEE 1394通信协议和使用以太网通信协议的网络通过总线传送数据。 新颖的数据传输方法有利地最小化主计算机处理器在数据传输的管理中的参与，从而使主机处理器的可用性最大化以执行其他计算。 具体地说，为了将数据从外围设备传送到网络，主机处理器生成数据指针表并将其发送到网络设备。 然后，网络设备中的处理器接管数据传输管理，使用数据指针表中的信息来定位并将指定的数据块从外围设备发送到网络。 在另一个实施例中，本发明确定要传送的数据块的大小是否超过总线或网络使用的相关通信协议的最大分组大小。 如果存在并超出这种限制，则将待传送的数据分成多个分组，使得每个分组符合限制协议的最大分组大小。 然后，迭代地传送较小的分组，直到整个数据块被传送。 因此，本发明消除了不同通信协议之间的分组大小差异所引起的不兼容性问题。

公开(公告)号：US6115760A

公开(公告)日：2000-09-05

申请号：US138943

申请日：1998-08-24

申请人： Burton B. Lo ,  Anthony L. Pan

发明人： Burton B. Lo ,  Anthony L. Pan

IPC分类号： G06F5/08 ,  G06F13/40 ,  G06F5/06 ,  G06F5/01 ,  G06F12/00

CPC分类号： G06F5/08 ,  G06F13/4004 ,  G06F2205/126 ,  G06F5/12

摘要： The circuit provides a scaleable buffer coupled between digital domains that require data buffering because they operate at different data transfer rates and/or because one or more of the digital domains uses data bursting. The scaleable buffer circuit does not have a large fixed throughput latency as is characteristic of a first-in-first-out buffer. The buffer includes serially coupled burst cells each having a sequential element, a controlled multiplexer and control logic for controlling the multiplexer and for generating output control signals. In one embodiment, the control circuit is a finite state machine. Each burst cell is capable of receiving data from an upstream burst cell or from the input data bus. Therefore, the buffer can be filled starting from its most downstream and vacant burst cell rather than always starting from the most upstream cell (as in a typical FIFO). This reduces the throughput latency of the buffer in cases when it is not always full. By using burst cells, rather than a dual ported RAM, the interface circuitry is significantly reduced in complexity. Each burst cell is uniform in construction and contains distributed interface circuitry making the circuit readily scaleable in size without redesigning the interface circuitry.

摘要翻译： 该电路提供耦合在需要数据缓冲的数字域之间的可扩展缓冲器，因为它们以不同的数据传输速率操作和/或因为一个或多个数字域使用数据突发。 可扩展缓冲电路不像先入先出缓冲区的特征那样具有较大的固定吞吐量等待时间。 缓冲器包括串联连接的突发单元，每个单元具有顺序元件，用于控制多路复用器和产生输出控制信号的受控多路复用器和控制逻辑。 在一个实施例中，控制电路是有限状态机。 每个突发单元能够从上游突发单元或从输入数据总线接收数据。 因此，缓冲器可以从其最下游和空闲突发单元开始填充，而不是始终从最上游的单元开始（如在典型的FIFO中）。 这样会减少缓冲区的吞吐量等待时间，因为它并不总是满。 通过使用突发单元而不是双端口RAM，接口电路的复杂度显着降低。 每个突发单元在结构上是均匀的，并且包含分布式接口电路，使得电路容易在尺寸上缩放，而无需重新设计接口电路。

公开(公告)号：US06452938B1

公开(公告)日：2002-09-17

申请号：US09031265

申请日：1998-02-26

申请人： Marwan A. Fawal ,  Burton B. Lo ,  Anthony L. Pan ,  George Kwan

发明人： Marwan A. Fawal ,  Burton B. Lo ,  Anthony L. Pan ,  George Kwan

IPC分类号： H04L1266

CPC分类号： H04L43/50

摘要： A system for reducing electromagnetic interference emissions is described. The system can include a network interface card with an Ethernet controller circuit. The Ethernet controller circuit generates an Ethernet output signal that includes a pre-emphasis component and a data component. The Ethernet controller circuit monitors the Ethernet output signal and adjusts the levels of the pre-emphasis component and the data component to reduce the electromagnetic interference caused by the network interface card but still fit the requirements for valid Ethernet signals.

摘要翻译： 描述了用于减少电磁干扰发射的系统。 该系统可以包括具有以太网控制器电路的网络接口卡。 以太网控制器电路产生包括预加重组件和数据组件的以太网输出信号。 以太网控制器电路监视以太网输出信号，并调整预加重组件和数据组件的电平，以减少网络接口卡引起的电磁干扰，但仍符合有效的以太网信号要求。

公开(公告)号：US06425071B1

公开(公告)日：2002-07-23

申请号：US09303890

申请日：1999-05-03

申请人： Burton B. Lo ,  Anthony L. Pan

发明人： Burton B. Lo ,  Anthony L. Pan

IPC分类号： G06F1300

CPC分类号： G06F13/4243 ,  G06F13/405

摘要： A method and apparatus to bridge between the PCI bus and a RISC processor interface bus. In one embodiment, the present invention is a single-ASIC implementation rather than a design using multiple discrete circuit components. The invention incorporates a method and apparatus that will minimize subsystem latencies and inefficiencies in order to maximize data throughput and system performance. In yet another embodiment, the RISC processor interface bus is the AMBA ASB bus. The invention further provides an Advanced RISC Machine interface bus unit which uses an improved clock crossing handshake mechanism that can support a range of clock frequencies on the AMBA ASB bus.

摘要翻译： 一种在PCI总线和RISC处理器接口总线之间桥接的方法和装置。 在一个实施例中，本发明是单ASIC实现，而不是使用多个分立电路组件的设计。 本发明结合了一种方法和装置，其将使子系统延迟和低效率最小化，以最大化数据吞吐量和系统性能。 在另一个实施例中，RISC处理器接口总线是AMBA ASB总线。 本发明还提供了一种高级RISC机器接口总线单元，其使用可以支持AMBA ASB总线上的时钟频率范围的改进的时钟跨越握手机制。