公开(公告)号：US08225245B2

公开(公告)日：2012-07-17

申请号：US12609370

申请日：2009-10-30

Applicant: Aravind Oommen ,  Hemanga Das ,  Krishnan Sundaresan

Inventor： Aravind Oommen ,  Hemanga Das ,  Krishnan Sundaresan

IPC: G06F9/45

CPC classification number: G06F17/505 ,  G06F2217/78

Abstract: A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions.

Abstract translation: 在半导体设计中合并门控时钟域的方法和系统包括：对初始的时钟选通功能集合中的时钟门控功能的每个子集产生一组定量的函数，其通过存在量化子集中的每个时钟门控函数产生 一组不是子集的其他时钟门控功能的支持集的一部分的变量。 如果一组量化函数相等，则选择一个作为超时钟门控功能，并将其添加到一组超时钟门控功能。 该超级时钟门控功能集合根据标准进行排序，并选择最佳选项并将其添加到最终时钟门控功能组中。 剩余的超级时钟门控功能被修改，以防止由所选择的超级时钟门控功能选通的触发器被剩余的超时钟门控功能选通。

公开(公告)号：US08533648B2

公开(公告)日：2013-09-10

申请号：US12779891

申请日：2010-05-13

Applicant: Krishnan Sundaresan ,  Aravind Oommen

Inventor： Krishnan Sundaresan ,  Aravind Oommen

IPC: G06F17/50

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/3275 ,  Y02D10/128 ,  Y02D10/14

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a description of a circuit that includes clocked memory elements, some of which are clock-gated. Next, the system identifies a sender memory element by identifying a sender path from an output of the sender memory element to a data input for a seed memory element. Then, the system identifies an enable-generating memory element by identifying an enable-signal path from an output of the enable-generating memory element to an enable signal which is used to gate a clock signal input for the seed memory element. Next, the system provides clock-gating for the sender memory element by generating an enable signal using a data input for the enable-generating memory element. Finally, the system gates a clock signal for the sender memory element using this generated enable signal.

Abstract translation: 本发明的实施例提供了一种用于时钟门控电路的方法和系统。 在操作期间，系统接收包括时钟存储器元件的电路的描述，其中一些是时钟门控的。 接下来，系统通过识别从发送者存储器元件的输出到种子存储器元件的数据输入的发送器路径来识别发送者存储器元件。 然后，该系统通过从使能产生存储器元件的输出识别使能信号路径识别出使能信号路径，该使能信号路径被用于对输入种子存储器元件的时钟信号进行选通。 接下来，系统通过使用用于产生能量的存储器元件的数据输入产生使能信号来为发送器存储器元件提供时钟门控。 最后，系统使用该产生的使能信号来为发送器存储元件门控一个时钟信号。

公开(公告)号：US20110283125A1

公开(公告)日：2011-11-17

申请号：US12779891

申请日：2010-05-13

Applicant: Krishnan Sundaresan ,  Aravind Oommen

Inventor： Krishnan Sundaresan ,  Aravind Oommen

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/3275 ,  Y02D10/128 ,  Y02D10/14

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a description of a circuit that includes clocked memory elements, some of which are clock-gated. Next, the system identifies a sender memory element by identifying a sender path from an output of the sender memory element to a data input for a seed memory element. Then, the system identifies an enable-generating memory element by identifying an enable-signal path from an output of the enable-generating memory element to an enable signal which is used to gate a clock signal input for the seed memory element. Next, the system provides clock-gating for the sender memory element by generating an enable signal using a data input for the enable-generating memory element. Finally, the system gates a clock signal for the sender memory element using this generated enable signal.

Abstract translation: 本发明的实施例提供了一种用于时钟门控电路的方法和系统。 在操作期间，系统接收包括时钟存储器元件的电路的描述，其中一些是时钟门控的。 接下来，系统通过识别从发送者存储器元件的输出到种子存储器元件的数据输入的发送器路径来识别发送者存储器元件。 然后，该系统通过从使能产生存储器元件的输出识别使能信号路径识别出使能信号路径，该使能信号路径被用于对输入种子存储器元件的时钟信号进行选通。 接下来，系统通过使用用于产生能量的存储器元件的数据输入产生使能信号来为发送器存储器元件提供时钟门控。 最后，系统使用该产生的使能信号来为发送器存储元件门控一个时钟信号。

公开(公告)号：US08132144B2

公开(公告)日：2012-03-06

申请号：US12486171

申请日：2009-06-17

Applicant: Krishnan Sundaresan ,  Aravind Oommen

Inventor： Krishnan Sundaresan ,  Aravind Oommen

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/14

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a circuit which includes a plurality of clocked memory elements. Next, the system identifies a feedback path from an output of a clocked memory element to an input of the clocked memory element, wherein the feedback path passes through intervening combinational logic, but does not pass through other clocked memory elements in the circuit. Then, the system gates a clock signal to the clocked memory element so that the clock signal is disabled when the feedback path causes a value which appears at the output of the clocked memory element to be appear at the input of the clocked memory element.

Abstract translation: 本发明的实施例提供了一种用于时钟门控电路的方法和系统。 在操作期间，系统接收包括多个计时存储元件的电路。 接下来，系统识别从时钟存储元件的输出到时钟控制的存储器元件的输入的反馈路径，其中反馈路径通过中间组合逻辑，但不通过电路中的其它时钟存储元件。 然后，系统将时钟信号向定时存储元件施加门限，使得当反馈路径导致出现在时钟存储器元件的输出处的值出现在时钟控制的存储器元件的输入端时，时钟信号被禁止。

公开(公告)号：US20100325452A1

公开(公告)日：2010-12-23

申请号：US12486171

申请日：2009-06-17

Applicant: Krishnan Sundaresan ,  Aravind Oommen

Inventor： Krishnan Sundaresan ,  Aravind Oommen

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/14

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a circuit which includes a plurality of clocked memory elements. Next, the system identifies a feedback path from an output of a clocked memory element to an input of the clocked memory element, wherein the feedback path passes through intervening combinational logic, but does not pass through other clocked memory elements in the circuit. Then, the system gates a clock signal to the clocked memory element so that the clock signal is disabled when the feedback path causes a value which appears at the output of the clocked memory element to be appear at the input of the clocked memory element.

Abstract translation: 本发明的实施例提供了一种用于时钟门控电路的方法和系统。 在操作期间，系统接收包括多个计时存储元件的电路。 接下来，系统识别从时钟存储元件的输出到时钟控制的存储器元件的输入的反馈路径，其中反馈路径通过中间组合逻辑，但不通过电路中的其它时钟存储元件。 然后，系统将时钟信号向定时存储元件施加门限，使得当反馈路径导致出现在时钟存储器元件的输出处的值出现在时钟控制的存储器元件的输入端时，时钟信号被禁止。

公开(公告)号：US20110107289A1

公开(公告)日：2011-05-05

申请号：US12609370

申请日：2009-10-30

Applicant: Aravind Oommen ,  Hemanga Das ,  Krishnan Sundaresan

Inventor： Aravind Oommen ,  Hemanga Das ,  Krishnan Sundaresan

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/78

Abstract: A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions.

Abstract translation: 在半导体设计中合并门控时钟域的方法和系统包括：对初始的时钟选通功能集合中的时钟门控功能的每个子集产生一组定量的函数，其通过存在量化子集中的每个时钟门控函数产生 一组不是子集的其他时钟门控功能的支持集的一部分的变量。 如果一组量化函数相等，则选择一个作为超时钟门控功能，并将其添加到一组超时钟门控功能。 该超级时钟门控功能集合根据标准进行排序，并选择最佳选项并将其添加到最终时钟门控功能组中。 剩余的超级时钟门控功能被修改，以防止由所选择的超级时钟门控功能选通的触发器被剩余的超时钟门控功能选通。