公开(公告)号：US20160098047A1

公开(公告)日：2016-04-07

申请号：US14509039

申请日：2014-10-07

申请人： Kumar Abhishek ,  Aniruddha Gupta ,  Sunny Gupta ,  Nitin Pant

发明人： Kumar Abhishek ,  Aniruddha Gupta ,  Sunny Gupta ,  Nitin Pant

IPC分类号： G05F1/46 ,  H03M1/66

CPC分类号： G05F1/462

摘要： An integrated circuit (IC) includes a digital-to-analog converter (DAC), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (LVD) and low voltage warning (LVW) circuits that generate LVD and LVW reference voltage signals. The controller generates and stores a voltage margin word (a difference between first and second DAC words that correspond to the LVD and LVW reference voltage signals, respectively). The controller compares the voltage margin word with predetermined maximum and minimum voltage margin words. If the voltage margin word does not lie between the predetermined maximum and minimum voltage margin words, the controller generates a voltage trimming signal that scales the LVW reference voltage signal. After scaling, if the voltage margin word lies between the predetermined maximum and minimum voltage margin words, the controller generates a calibration pass signal, otherwise the controller generates a calibration fail signal.

摘要翻译： 集成电路（IC）包括数模转换器（DAC），电压监视电路和控制器。 电压监控电路包括产生LVD和LVW参考电压信号的低电压检测（LVD）和低电压警告（LVW）电路。 控制器产生并存储电压裕度字（分别对应于LVD和LVW参考电压信号的第一和第二DAC字之间的差异）。 控制器将电压裕度字与预定的最大和最小电压裕度字进行比较。 如果电压裕度字不在预定的最大和最小电压裕度字之间，则控制器产生缩放LVW参考电压信号的电压调整信号。 在缩放之后，如果电压裕度字位于预定的最大和最小电压裕度字之间，则控制器产生校准通过信号，否则控制器产生校准失败信号。

公开(公告)号：US09383759B2

公开(公告)日：2016-07-05

申请号：US14509039

申请日：2014-10-07

申请人： Kumar Abhishek ,  Aniruddha Gupta ,  Sunny Gupta ,  Nitin Pant

发明人： Kumar Abhishek ,  Aniruddha Gupta ,  Sunny Gupta ,  Nitin Pant

IPC分类号： G05F1/46

CPC分类号： G05F1/462

摘要： An integrated circuit (IC) includes a digital-to-analog converter (DAC), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (LVD) and low voltage warning (LVW) circuits that generate LVD and LVW reference voltage signals. The controller generates and stores a voltage margin word (a difference between first and second DAC words that correspond to the LVD and LVW reference voltage signals, respectively). The controller compares the voltage margin word with predetermined maximum and minimum voltage margin words. If the voltage margin word does not lie between the predetermined maximum and minimum voltage margin words, the controller generates a voltage trimming signal that scales the LVW reference voltage signal. After scaling, if the voltage margin word lies between the predetermined maximum and minimum voltage margin words, the controller generates a calibration pass signal, otherwise the controller generates a calibration fail signal.

摘要翻译： 集成电路（IC）包括数模转换器（DAC），电压监视电路和控制器。 电压监控电路包括产生LVD和LVW参考电压信号的低电压检测（LVD）和低电压警告（LVW）电路。 控制器产生并存储电压裕度字（分别对应于LVD和LVW参考电压信号的第一和第二DAC字之间的差异）。 控制器将电压裕度字与预定的最大和最小电压裕度字进行比较。 如果电压裕度字不在预定的最大和最小电压裕度字之间，则控制器产生缩放LVW参考电压信号的电压调整信号。 在缩放之后，如果电压裕度字位于预定的最大和最小电压裕度字之间，则控制器产生校准通过信号，否则控制器产生校准失败信号。

公开(公告)号：US09494969B2

公开(公告)日：2016-11-15

申请号：US14457133

申请日：2014-08-12

申请人： Aniruddha Gupta ,  Akshay K. Pathak ,  Garima Sharda ,  Nidhi Sinha

发明人： Aniruddha Gupta ,  Akshay K. Pathak ,  Garima Sharda ,  Nidhi Sinha

IPC分类号： H03L7/00 ,  G06F1/12

CPC分类号： G06F1/12 ,  G06F1/08 ,  G06F1/24

摘要： An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.

摘要翻译： 用于片上系统（SOC）的板上复位电路解决了当不同的电源域或复位域从不同的源接收复位时出现的异步复位时触发器的元稳定性问题。 为了改善这个问题，在时钟门控时，复位信号被断言和解除断言。 在断言（或解除断言）之后，重新设置时钟的最小时间，以便具有同步复位的逻辑也可以接收复位。

公开(公告)号：US11546552B1

公开(公告)日：2023-01-03

申请号：US17468650

申请日：2021-09-07

申请人： Aniruddha Gupta ,  Arulita Gupta ,  Preeti Gupta ,  Kishor Kumar Gupta

发明人： Aniruddha Gupta ,  Arulita Gupta ,  Preeti Gupta ,  Kishor Kumar Gupta

IPC分类号： H04L51/48 ,  H04L67/54 ,  H04N7/15 ,  G06F3/0482 ,  G06F3/04817

摘要： A system and method for real-life interactive experience between virtual participants in a gathering of up to thousands of people attending a streamed event, using their computers and mobile devices. The virtual participants sit at boxes and tables at the event and see video and hear audio of other participants sitting at the same table and box. The participants interact with other participants of their choosing without disturbing the rest of the participants. They can use local chat boxes and global chat boxes to chat with the participants of the event. The participants may virtually move from one area to another area of the event using the event layout and sit in a new area of their choosing as they would at an in-person event while watching the streaming of the event thus providing a close to real-life experience of interacting with the event participants.