公开(公告)号：US06288947B1

公开(公告)日：2001-09-11

申请号：US09604687

申请日：2000-06-27

申请人： Kwan-Weon Kim ,  Dong-Sik Jeong

发明人： Kwan-Weon Kim ,  Dong-Sik Jeong

IPC分类号： G11C710

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C11/4093 ,  G11C11/4096

摘要： A memory device having a plurality of pipelatch circuits storing data from memory cells via global input/output lines, a pipelatch input control circuit to selectively couple the pipelatch circuit to the global input/output lines in response to a pipelatch control signal, and a pipe count signal generator to control a data path between the pipelatch circuits and an output driver, wherein the pipelatch input control circuit includes: a first control signal generator receiving a first control signal and global input/output line signals and producing a pass gate control signal; a second control signal generator receiving the first control signal and the pass gate control signal and producing a plurality of second control signals; a third control signal generator receiving the pass gate control signal and producing a third control signal by combining the pass gate control signal and a delay signal of the pass gate control signal; and a fourth control signal generator receiving the first control signal, the plurality of second control signals and the third control signal and producing the pipelatch control signal.

摘要翻译： 一种存储装置，其具有多个管线电路，其经由全局输入/输出线路存储来自存储器单元的数据;管线输入控制电路，用于响应于管线分配控制信号选择性地将管线电路耦合到全局输入/输出线;以及管 计数信号发生器，用于控制所述管线电路和输出驱动器之间的数据路径，其中所述管道输送控制电路包括：第一控制信号发生器，接收第一控制信号和全局输入/输出线路信号并产生通过门控制信号; 接收第一控制信号和通过门控制信号并产生多个第二控制信号的第二控制信号发生器; 接收所述通过栅极控制信号并通过组合所述通过栅极控制信号和所述通过栅极控制信号的延迟信号而产生第三控制信号的第三控制信号发生器; 以及第四控制信号发生器，接收第一控制信号，多个第二控制信号和第三控制信号，并产生管线控制信号。