公开(公告)号：US20090194817A1

公开(公告)日：2009-08-06

申请号：US12420936

申请日：2009-04-09

申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

IPC分类号： H01L27/092 ,  H01L23/48

CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

摘要翻译： 形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。 覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第 具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。 然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。 此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

公开(公告)号：US20080242015A1

公开(公告)日：2008-10-02

申请号：US11691691

申请日：2007-03-27

申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

摘要翻译： 形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。 覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第 具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。 然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。 此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

公开(公告)号：US07800134B2

公开(公告)日：2010-09-21

申请号：US12420936

申请日：2009-04-09

申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

IPC分类号： H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

摘要翻译： 形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。 覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第 具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。 然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。 此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

公开(公告)号：US07534678B2

公开(公告)日：2009-05-19

申请号：US11691691

申请日：2007-03-27

申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

摘要翻译： 形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。 覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第 具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。 然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。 此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

公开(公告)号：US20090124093A1

公开(公告)日：2009-05-14

申请号：US12353519

申请日：2009-01-14

申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

IPC分类号： H01L21/469

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。 提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。 特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

公开(公告)号：US20080116521A1

公开(公告)日：2008-05-22

申请号：US11560564

申请日：2006-11-16

申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

IPC分类号： H01L27/088 ,  H01L21/77

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。 提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。 特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

公开(公告)号：US07781276B2

公开(公告)日：2010-08-24

申请号：US12353519

申请日：2009-01-14

申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

IPC分类号： H01L21/337

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。 提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。 特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

公开(公告)号：US07687915B2

公开(公告)日：2010-03-30

申请号：US12216097

申请日：2008-06-30

申请人： Kyoung-woo Lee ,  Hong-jae Shin

发明人： Kyoung-woo Lee ,  Hong-jae Shin

IPC分类号： H01L23/522

CPC分类号： H01L23/585 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.

摘要翻译： 示例实施例涉及具有单体裂纹停止结构的半导体器件，其被配置为减少或防止裂纹扩展和/或湿气穿透。 根据示例性实施例的半导体衬底可以包括有源区和围绕有源区的裂纹停止区。 层间绝缘层可以顺序堆叠在半导体衬底上。 层间绝缘层可以包括第一双镶嵌图案和第一开口。 可以在层间绝缘层中形成第一双镶嵌图案，以便在暴露半导体基板的第一部分的同时垂直于半导体基板的表面。 第一开口可以形成在裂纹停止区域中并且可以延伸穿过层间绝缘层以暴露半导体衬底的第二部分。 第一双镶嵌金属布线可以形成在第一双镶嵌图案中并且可以接触半导体基板的暴露的第一部分。 可以在第一开口中形成单体第一裂纹阻挡结构，以与半导体衬底的暴露的第二部分接触。

公开(公告)号：US07598168B2

公开(公告)日：2009-10-06

申请号：US11033208

申请日：2005-01-11

申请人： Sang-cheol Han ,  Kyoung-woo Lee ,  Mi-young Kim

发明人： Sang-cheol Han ,  Kyoung-woo Lee ,  Mi-young Kim

IPC分类号： H01L21/4763 ,  H01L21/461

CPC分类号： H01L21/76808 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76829

摘要： A method of forming a dual damascene semiconductor interconnection and an etchant composition specially adapted for stripping a sacrificial layer in a dual damascene fabrication process without profile damage to a dual damascene pattern are provided. The method includes sequentially forming a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer on a surface of a semiconductor substrate on which a lower metal wiring is formed; etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; forming a sacrificial layer within the via; etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; removing the sacrificial layer remaining around the via using an etchant composition including NH4F, HF, H2O and a surfactant; and forming an upper metal wiring within the thus formed dual damascene pattern including the via and the trench. The preferred etchant composition for stripping a sacrificial layer in the foregoing dual damascene process consists essentially of NH4F, HF, H2O and a surfactant.

摘要翻译： 提供了形成双镶嵌半导体互连的方法和特别适于在双镶嵌制造工艺中剥离牺牲层而不对双镶嵌图案造成损伤的蚀刻剂组合物。 该方法包括在其上形成有下金属布线的半导体衬底的表面上顺序地形成第一蚀刻停止层，第一金属间电介质，第二金属间电介质和覆盖层; 蚀刻第一金属间电介质，第二金属间电介质和封盖层以形成通孔; 在通孔内形成牺牲层; 蚀刻牺牲层，第二金属间电介质和覆盖层以形成沟槽; 使用包括NH 4 F，HF，H 2 O和表面活性剂的蚀刻剂组合物除去残留在通孔周围的牺牲层; 以及在由此形成的包括通孔和沟槽的双镶嵌图案中形成上金属布线。 用于剥离前述双镶嵌工艺中的牺牲层的优选蚀刻剂组合物基本上由NH 4 F，HF，H 2 O和表面活性剂组成。

公开(公告)号：US20090096104A1

公开(公告)日：2009-04-16

申请号：US12216097

申请日：2008-06-30

申请人： Kyoung-woo Lee ,  Hong-jae Shin

发明人： Kyoung-woo Lee ,  Hong-jae Shin

IPC分类号： H01L23/532

CPC分类号： H01L23/585 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.

摘要翻译： 示例实施例涉及具有单体裂纹停止结构的半导体器件，其被配置为减少或防止裂纹扩展和/或湿气穿透。 根据示例性实施例的半导体衬底可以包括有源区和围绕有源区的裂纹停止区。 层间绝缘层可以顺序堆叠在半导体衬底上。 层间绝缘层可以包括第一双镶嵌图案和第一开口。 可以在层间绝缘层中形成第一双镶嵌图案，以便在暴露半导体基板的第一部分的同时垂直于半导体基板的表面。 第一开口可以形成在裂纹停止区域中并且可以延伸穿过层间绝缘层以暴露半导体衬底的第二部分。 第一双镶嵌金属布线可以形成在第一双镶嵌图案中并且可以接触半导体基板的暴露的第一部分。 可以在第一开口中形成单体第一裂纹阻挡结构，以与半导体衬底的暴露的第二部分接触。