公开(公告)号：US20120313693A1

公开(公告)日：2012-12-13

申请号：US13491110

申请日：2012-06-07

申请人： Kyung Tae Do ,  Hyung Ock Kim ,  Hyo Sig Won ,  Jung Yun Choi

发明人： Kyung Tae Do ,  Hyung Ock Kim ,  Hyo Sig Won ,  Jung Yun Choi

IPC分类号： G05F3/02

CPC分类号： G06F1/26 ,  G06F1/04 ,  G06F1/32

摘要： A method of controlling the provision of a body bias voltage to a logic gate region of a semiconductor device includes; gating application of a clock signal applied to a synchronization element in the logic gate region in accordance with an enable signal, and providing the body bias voltage to each body terminal of a plurality of logic gates arranged in the logic gate region in accordance with the enable signal.

摘要翻译： 控制向半导体器件的逻辑栅极区域提供体偏置电压的方法包括： 根据使能信号门控施加到逻辑门区域中的同步元件的时钟信号，并根据该使能信号向布置在逻辑门区域中的多个逻辑门极的每个主体端子提供体偏置电压 信号。

公开(公告)号：US20100058258A1

公开(公告)日：2010-03-04

申请号：US12547729

申请日：2009-08-26

申请人： Kyung Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

发明人： Kyung Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced.

摘要翻译： 在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际漏电特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中每个单元的虚拟单元泄漏特性函数进行算术运算来产生段泄漏特性函数。 然后，通过统计操作芯片中每个段的段泄漏特性函数来产生全片泄漏特性函数。 因此，威尔金森的用于产生全芯片泄漏特性函数的方法的计算量可以显着降低。

公开(公告)号：US07984404B2

公开(公告)日：2011-07-19

申请号：US11934252

申请日：2007-11-02

申请人： Kyung Tae Do ,  Young Hwan Kim ,  Haeng Seon Son

发明人： Kyung Tae Do ,  Young Hwan Kim ,  Haeng Seon Son

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： Provided is a black box timing modeling method for a digital circuit comprising synchronous elements including latches. The method includes: characterizing a setup time arc by extracting a setup time with respect to a rising or falling edge of a clock of a synchronous element with respect to an input connected to the synchronous element and forming the setup time arc using the extracted setup time; and characterizing a clock-to-output delay arc by providing information on an output departure time from an output based on a rising or falling edge of a clock of a closest synchronous element connected to the output, at least partially based on the setup time arc and forming the clock-to-output delay arc. Accordingly, the method can be efficiently used for a latch-based design without re-verifying internal components of the latch-based design during an upper-level verification, thereby reducing verification time and model size.

摘要翻译： 提供了一种用于数字电路的黑盒定时建模方法，包括具有锁存器的同步元件。 该方法包括：通过相对于连接到同步元件的输入提取相对于同步元件的时钟的上升沿或下降沿的建立时间来表征建立时间弧，并使用所提取的建立时间来形成建立时间弧 ; 以及通过基于建立时间弧至少部分地基于连接到输出的最近同步元件的时钟的上升沿或下降沿从输出提供关于输出离开时间的信息来表征时钟到输出延迟弧 并形成时钟到输出的延迟电弧。 因此，该方法可以有效地用于基于锁存器的设计，而不会在上级验证期间重新验证基于锁存器的设计的内部部件，从而减少验证时间和型号尺寸。