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    Method of estimating a leakage current in a semiconductor device
    1.
    发明授权
    Method of estimating a leakage current in a semiconductor device 有权
    估计半导体器件中漏电流的方法

    公开(公告)号：US08156460B2

    公开(公告)日：2012-04-10

    申请号：US12547729

    申请日：2009-08-26

    申请人： Kyung-Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    发明人： Kyung-Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.

    摘要翻译： 在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际泄漏特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中所有单元的虚拟单元泄漏特性函数进行算术运算，产生段的段泄漏特性函数。 然后，通过统计操作芯片中所有段的段泄漏特性函数来产生芯片的全芯片泄漏特性功能。 因此，Wilkinson用于产生全芯片泄漏特性功能的方法的计算负载可以显着降低。

    Method of Estimating a Leakage Current in a Semiconductor Device
    2.
    发明申请
    Method of Estimating a Leakage Current in a Semiconductor Device 有权
    估算半导体器件中泄漏电流的方法

    公开(公告)号：US20100058258A1

    公开(公告)日：2010-03-04

    申请号：US12547729

    申请日：2009-08-26

    申请人： Kyung Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    发明人： Kyung Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced.

    摘要翻译： 在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际漏电特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中每个单元的虚拟单元泄漏特性函数进行算术运算来产生段泄漏特性函数。 然后，通过统计操作芯片中每个段的段泄漏特性函数来产生全片泄漏特性函数。 因此，威尔金森的用于产生全芯片泄漏特性函数的方法的计算量可以显着降低。

    Method of incremental statistical static timing analysis based on timing yield
    3.
    发明授权
    Method of incremental statistical static timing analysis based on timing yield 有权
    基于定时收益的增量统计静态时序分析方法

    公开(公告)号：US08046725B2

    公开(公告)日：2011-10-25

    申请号：US12475545

    申请日：2009-05-31

    申请人： Jinwook Kim ,  Young Hwan Kim ,  Wook Kim

    发明人： Jinwook Kim ,  Young Hwan Kim ,  Wook Kim

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA; a second step in which, if a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; and a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node.

    摘要翻译： 提供了数字电路的增量SSTA（统计静态时序分析）的方法，该方法包括第一步骤，其中当在数字电路中替换门时，从更换的门的节点执行延迟传播 基于SSTA的虚拟汇聚节点; 第二步骤，如果在向虚拟汇聚节点传播延迟的每个门的门定时收益的改变值小于预定阈值，则停止相对于相应门的扇出门的延迟传播; 以及第三步骤，当相对于所替换的门的节点的延迟传播到虚拟宿节点时，在虚拟宿节点处计算新的定时收益。

    METHOD OF TIMING CRITICALITY CALCULATION FOR STATISTICAL TIMING OPTIMIZATION OF VLSI CIRCUIT
    4.
    发明申请
    METHOD OF TIMING CRITICALITY CALCULATION FOR STATISTICAL TIMING OPTIMIZATION OF VLSI CIRCUIT 有权
    定时关键度计算方法对VLSI电路的统计时序优化

    公开(公告)号：US20100242006A1

    公开(公告)日：2010-09-23

    申请号：US12474547

    申请日：2009-05-29

    申请人： Hyoun Soo Park ,  Young Hwan Kim ,  Dai Joon Hyun ,  Wook Kim

    发明人： Hyoun Soo Park ,  Young Hwan Kim ,  Dai Joon Hyun ,  Wook Kim

    IPC分类号： G06F17/10

    CPC分类号： G06F17/5031 ,  G06F17/505

    摘要： Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.

    摘要翻译： 提供了一种优化积分电路的统计定时的方法，该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化，以ADD操作和基于块的统计静态的MAX操作 时序分析（SSTA）方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值，计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。 因此，基于统计静态时序分析（SSTA）的ADD操作和MAX操作的线性近似来计算定时收益关键性，因此计算复杂度相对于总节点数是线性的，关键节点显着影响定时收益 可以更准确地提取电路。

    Method of timing criticality calculation for statistical timing optimization of VLSI circuit
    5.
    发明授权
    Method of timing criticality calculation for statistical timing optimization of VLSI circuit 有权
    VLSI电路统计时序优化的定时临界计算方法

    公开(公告)号：US08046724B2

    公开(公告)日：2011-10-25

    申请号：US12474547

    申请日：2009-05-29

    申请人： Hyoun Soo Park ,  Young Hwan Kim ,  Dai Joon Hyun ,  Wook Kim

    发明人： Hyoun Soo Park ,  Young Hwan Kim ,  Dai Joon Hyun ,  Wook Kim

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505

    摘要： Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.

    摘要翻译： 提供了一种优化集成电路的统计定时的方法，该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化，以ADD操作和基于块的统计静态的MAX操作 时序分析（SSTA）方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值，计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。 因此，基于统计静态时序分析（SSTA）的ADD操作和MAX操作的线性近似来计算定时收益关键性，因此计算复杂度相对于总节点数是线性的，关键节点显着影响定时收益 可以更准确地提取电路。

    METHOD OF INCREMENTAL STATISTICAL STATIC TIMING ANALYSIS BASED ON TIMING YIELD
    6.
    发明申请
    METHOD OF INCREMENTAL STATISTICAL STATIC TIMING ANALYSIS BASED ON TIMING YIELD 有权
    基于时序的增量统计静态时序分析方法

    公开(公告)号：US20100306724A1

    公开(公告)日：2010-12-02

    申请号：US12475545

    申请日：2009-05-31

    申请人： Jinwook Kim ,  Young Hwan Kim ,  Wook Kim

    发明人： Jinwook Kim ,  Young Hwan Kim ,  Wook Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA; a second step in which, if a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; and a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node.

    摘要翻译： 提供了数字电路的增量SSTA（统计静态时序分析）的方法，该方法包括第一步骤，其中当在数字电路中替换门时，从更换的门的节点执行延迟传播 基于SSTA的虚拟汇聚节点; 第二步骤，如果在向虚拟汇聚节点传播延迟的每个门的门定时收益的改变值小于预定阈值，则停止相对于相应门的扇出门的延迟传播; 以及第三步骤，当相对于所替换的门的节点的延迟传播到虚拟宿节点时，在虚拟宿节点处计算新的定时收益。

    Display device and blower thereof
    7.
    发明授权
    Display device and blower thereof 有权
    显示装置及鼓风机

    公开(公告)号：US07522416B2

    公开(公告)日：2009-04-21

    申请号：US11318549

    申请日：2005-12-28

    申请人： Wook Kim ,  Jun Ho Bae ,  Chang Joon Kim

    发明人： Wook Kim ,  Jun Ho Bae ,  Chang Joon Kim

    IPC分类号： H05K7/20 ,  H05K5/00 ,  G02F1/1333

    CPC分类号： G02F1/133382 ,  G02F1/133385 ,  H05K7/20972

    摘要： A display device, and a blower thereof are disclosed. The display device includes an axial flow fan within a case, which has a display panel encased therein. The axial flow fan is provided in a width direction within the case, so that, while being rotated within the case, the axial flow fan generates forced air flow suitable to the case. The forced air flow is generated in a forward direction along with air flow by natural convection within the case.

    摘要翻译： 公开了一种显示装置及其鼓风机。 显示装置包括壳体内的轴流式风扇，其具有封装在其中的显示面板。 所述轴流风扇沿壳体内的宽度方向设置，使得在所述壳体内旋转的同时，所述轴流风扇产生适合于所述壳体的强制空气流。 通过箱内的自然对流，通过空气流向前进方向产生强制空气流。

    Cooling fan
    9.
    发明申请
    Cooling fan 有权
    冷风扇

    公开(公告)号：US20050271521A1

    公开(公告)日：2005-12-08

    申请号：US11020247

    申请日：2004-12-27

    申请人： Wook Kim ,  Chang-Jun Kim ,  Ho-Seon Rew

    发明人： Wook Kim ,  Chang-Jun Kim ,  Ho-Seon Rew

    IPC分类号： H04N5/74 ,  F04D29/38 ,  F04D29/54 ,  F04D29/66 ,  F04F1/06

    CPC分类号： F04D29/667 ,  F04D29/384 ,  F04D29/545

    摘要： Disclosed is a cooling fan including a fan rotated by a motor, for forcibly circulating the air, and a fan housing having a through hole with a predetermined inside diameter so that the fan can be mounted thereon. A curvature radius of the end of the inner circumference of the through hole sucking the air is smaller than a curvature radius of the end of the inner circumference of the through hole discharging the air. As a result, the cooling fan can minimize noises in the operation.

    摘要翻译： 公开了一种冷却风扇，其包括由电动机旋转的风扇，用于强制循环空气;以及风扇壳体，具有具有预定内径的通孔，从而风扇可以安装在其上。 吸入空气的通孔的内周的端部的曲率半径小于排出空气的通孔的内周的端部的曲率半径。 结果，冷却风扇可以最小化操作中的噪音。

    Semiconductor optical device and method for fabricating the same
    10.
    发明授权
    Semiconductor optical device and method for fabricating the same 有权

    公开(公告)号：US06337223B1

    公开(公告)日：2002-01-08

    申请号：US09351439

    申请日：1999-07-12

    申请人： Wook Kim ,  Tae Kyung Yoo

    发明人： Wook Kim ,  Tae Kyung Yoo

    IPC分类号： H01L2120

    CPC分类号： H01S5/02 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/10 ,  H01S5/0205 ,  H01S5/32341 ,  H01S2304/12

    摘要： A semiconductor optical device and a method for fabricating the same. The semiconductor optical device comprises a substrate, a semiconductor electrode layer of a first conductive type formed on the substrate and having a groove formed to a desired depth therein, a semiconductor layer of the first conductive type formed from side walls of the groove up to a part of the semiconductor electrode layer of the first conductive type on the periphery of the groove, a cladding layer of the first conductive type, an active layer of the first conductive type, a cladding layer of a second conductive type and a semiconductor electrode layer of the second conductive type sequentially formed on the semiconductor layer of the first conductive type, and electrodes of the first and second conductive types formed respectively on the semiconductor electrode layers of the first and second conductive types.