公开(公告)号：US20140021475A1

公开(公告)日：2014-01-23

申请号：US13717006

申请日：2012-12-17

Applicant: LG DISPLAY CO., LTD.

Inventor： Tae-Hyoung MOON ,  Kyu-Hwang LEE ,  Kyung-Ha LEE

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/786 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66765

Abstract: An array substrate for a display device includes an insulation substrate, a gate line formed on the insulation substrate, a data line crossing the gate line to define a pixel area, a thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode, a passivation layer covering the gate line, the data line and the thin film transistor and including a drain contact hole to expose the drain electrode, and a pixel electrode formed on the pixel area and being connected to the drain contact hole through the drain contact hole. Each of the data line, the source electrode and the drain electrode includes a lower layer having copper and an upper layer covering upper and side surfaces of the lower layer, and the upper layer is thinner than the lower layer.

Abstract translation: 用于显示装置的阵列基板包括绝缘基板，形成在绝缘基板上的栅极线，与栅极线交叉以限定像素区域的数据线，包括连接到栅极线的栅电极的薄膜晶体管，源极 连接到数据线的电极，漏电极，覆盖栅极线的钝化层，数据线和薄膜晶体管，并且包括漏极接触孔以暴露漏极;以及像素电极，形成在像素区域上，以及 通过漏极接触孔连接到漏极接触孔。 数据线，源电极和漏电极中的每一个包括具有铜的下层和覆盖下层的上表面和侧表面的上层，并且上层比下层薄。

公开(公告)号：US20150001543A1

公开(公告)日：2015-01-01

申请号：US14096932

申请日：2013-12-04

Applicant: LG DISPLAY CO., LTD.

Inventor： Tae-Hyoung MOON ,  Tae-Joon SONG ,  Kyu-Hwang LEE ,  Kyung-Ha LEE

IPC: H01L27/12

CPC classification number: H01L27/1244 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/1259

Abstract: An array substrate includes: a trench having a depth from a surface of a substrate; a gate line, a gate electrode and a data pattern filling the respective trenches, wherein the data pattern is between the adjacent gate lines; a gate insulating layer on the gate line, the gate electrode and the data pattern, substantially flat over the substrate, and including contact holes that expose both ends of the data pattern, respectively; a data connection portion on the gate insulating layer and contacting the adjacent data patterns through the contact holes; a source electrode extending from the data connection portion, and a drain electrode spaced apart from the source electrode; a passivation layer on the source and drain electrodes and including a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and contacting the drain electrode through the drain contact hole.

Abstract translation: 阵列基板包括：具有从基板的表面的深度的沟槽; 栅极线，栅极电极和填充各个沟槽的数据图案，其中数据图案位于相邻的栅极线之间; 栅极线上的栅极绝缘层，栅电极和数据图案在基板上基本平坦，并且包括分别暴露数据图案的两端的接触孔; 栅极绝缘层上的数据连接部分，并通过接触孔与相邻的数据图形接触; 从数据连接部分延伸的源电极和与源电极间隔开的漏电极; 源电极和漏电极上的钝化层，并且包括暴露漏电极的漏极接触孔; 以及钝化层上的像素电极，并通过漏极接触孔与漏电极接触。