公开(公告)号：US09450106B2

公开(公告)日：2016-09-20

申请号：US14750217

申请日：2015-06-25

Applicant: LG DISPLAY CO., LTD.

Inventor： Sang Kug Han ,  Ki Sul Cho ,  Choon Ho Park ,  Jin Ho Choi ,  Kuk Hwan Kim ,  Soo Hong Kim ,  Eun Ji Ham ,  Byoung Cheol Song

IPC: H01L29/04 ,  G09G3/36 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0692 ,  H01L29/42384 ,  H01L29/78609 ,  H01L29/78645 ,  H01L29/78648

Abstract: Disclosed is a thin film transistor (TFT) of a display apparatus which reduces a leakage current caused by a hump and decreases screen defects. The TFT includes an active layer and a first gate electrode with a gate insulator therebetween, and a source electrode and a drain electrode respectively disposed at both ends of the active layer. The gate electrode branches as a plurality of lines and overlaps the active layer. The active layer includes one or more channel areas between the source electrode and the drain electrode, one or more dummy areas, and a plurality of link areas between the one or more channel areas to connect the one or more channel areas in one pattern. A length of each of the one or more dummy areas extends from an edge of a corresponding channel area.

Abstract translation: 公开了一种显示装置的薄膜晶体管（TFT），其减少由隆起引起的漏电流并减少屏幕缺陷。 TFT包括有源层和在其之间具有栅极绝缘体的第一栅电极，以及分别设置在有源层的两端的源电极和漏电极。 栅极分支为多条线并与有源层重叠。 有源层包括在源电极和漏电极之间的一个或多个沟道区，一个或多个虚拟区，以及在一个或多个沟道区之间的多个连接区，用于以一个图案连接一个或多个沟道区。 一个或多个虚拟区域中的每一个的长度从对应的通道区域的边缘延伸。

公开(公告)号：US09934723B2

公开(公告)日：2018-04-03

申请号：US14739799

申请日：2015-06-15

Applicant: LG DISPLAY CO., LTD.

Inventor： Jung-Min Lee ,  Juhn Suk Yoo ,  Ji No Lee ,  Jae Soo Park ,  Chang Heon Kang ,  Ho Young Ko ,  Soo Hong Kim ,  Sung Ki Hong

IPC: G06F3/038 ,  G09G3/3233 ,  H01L27/32

CPC classification number: G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2300/0866 ,  G09G2380/02 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3279 ,  H01L2227/323 ,  H01L2227/326

Abstract: An electronic display panel comprising a plastic substrate; a bottom shield metal (BSM) on the plastic substrate; a thin-film transistor (TFT) on the BSM, the TFT and the BSM at least partially overlapping each other; and an active buffer layer between the TFT and the BSM, wherein the BSM is connected to one of a gate electrode, a source electrode, and a drain electrode of the TFT. A bottom shield metal (BSM) on the plastic substrate, the BSM located to minimize formation of a back channel in a pixel circuit by trapped charges of the plastic substrate, the pixel circuit in a pixel area defined by a gate line and a data line on the plastic substrate, the pixel circuit on the active buffer layer including a plurality of TFTs and a plurality of component interconnecting nodes.