公开(公告)号：US20140168554A1

公开(公告)日：2014-06-19

申请号：US14080809

申请日：2013-11-15

Applicant: LG DISPLAY CO., LTD.

Inventor： Kyung-Mo SON ,  Jae-Kyun LEE ,  Sung-Chol YI ,  Taek-Jun JUNG ,  Sun-Ju KU ,  Soon-Hwan HONG ,  Sang-Su JANG ,  Jun-Young JEONG ,  Eun-Hye LEE

IPC: G02F1/1343

CPC classification number: G02F1/134336 ,  G02F1/13394 ,  G02F1/134309 ,  G02F2001/13396

Abstract: An array substrate includes a substrate; gate lines over the substrate along a first direction; data lines over the substrate along a second direction and crossing the gate lines to define pixel regions; a thin film transistor at each crossing portion of the gate and data lines; an insulating layer covering the thin film transistor and having a flat top surface; a common electrode on the insulating layer all over the substrate; a common line on the common electrode; a passivation layer on the common line; and a pixel electrode on the passivation layer in each pixel region and connected to the thin film transistor, the pixel electrode including electrode patterns, wherein the passivation layer has a step height at a top surface of the passivation layer due to the plurality of common lines.

Abstract translation: 阵列基板包括基板; 沿着第一方向在基板上方的栅极线; 数据线沿着第二方向穿过衬底，并与栅极线交叉以限定像素区域; 栅极和数据线的每个交叉部分处的薄膜晶体管; 覆盖薄膜晶体管并具有平坦的顶表面的绝缘层; 在整个衬底上的绝缘层上的公共电极; 公共电极上的共同线路; 公共线上的钝化层; 以及像素电极，其在每个像素区域中的钝化层上并连接到所述薄膜晶体管，所述像素电极包括电极图案，其中所述钝化层由于所述多个公共线而在所述钝化层的顶表面处具有台阶高度 。