公开(公告)号：US20180144705A1

公开(公告)日：2018-05-24

申请号：US15807403

申请日：2017-11-08

Applicant: LG Display Co., Ltd.

Inventor： Chulwon LEE ,  Juyoung NOH

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G09G3/3225 ,  G09G2300/0452 ,  G09G2300/0819 ,  G09G2300/0876 ,  G09G2320/0204 ,  G09G2320/0209 ,  G09G2320/029 ,  G09G2320/0295 ,  G09G2320/045 ,  G09G2330/023 ,  G09G2330/12

Abstract: A display device and a method of driving the same are disclosed. The display device includes a display panel configured to display an image, and a parasitic capacitor compensation circuit including a compensation capacitor connected to a sensing line of the display panel and a control switch configured to perform a switching operation so that the compensation capacitor has a predetermined capacitance. The control switch is turned on in an image display operation of the display panel and is turned off in a sensing operation of the display panel.

公开(公告)号：US20170294159A1

公开(公告)日：2017-10-12

申请号：US15480121

申请日：2017-04-05

Applicant: LG Display Co., Ltd.

Inventor： Chulwon LEE ,  Seungtae KIM

IPC: G09G3/3233 ,  H01L27/32

CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2320/0295 ,  G09G2320/043 ,  G09G2320/0646 ,  G09G2320/0666 ,  G09G2320/0693 ,  H01L27/3248

Abstract: A current sensing unit can include a current sink circuit connected to a sensing line, which reduces a pixel current fed via the sensing line by an amount equal to a sink current; a current integrator connected to the sensing line, which accumulates an adjusted current from the sensing line and outputs an integrated value based on the pixel current minus the sink current; a sampling part that samples and holds the integrated value; and an analog-to-digital converter that converts the integrated value from an analog value to a digital sensed value.

公开(公告)号：US20170154573A1

公开(公告)日：2017-06-01

申请号：US15365200

申请日：2016-11-30

Applicant: LG DISPLAY CO., LTD.

Inventor： Kyoungdon WOO ,  Chulwon LEE ,  Myunggi LIM ,  Juyoung NOH

IPC: G09G3/3233 ,  G09G3/3266 ,  G09G3/3283

Abstract: An organic light-emitting display can include a display panel including sensing lines connected to pixels; a current integrator configured to receive current from a pixel through a sensing line connected to a first input terminal, receive a reference voltage through a reference voltage line connected to a second input terminal, and swap a path through which the current applied through the first input terminal flows and a path through which the reference voltage applied through the second input terminal is supplied; a sampling part including a first sample and hold circuit for sampling a first output voltage of the current integrator and a second sample and hold circuit for sampling a second output voltage of the current integrator, subsequent to the first output voltage, which outputs the first and second output voltages sampled by the first and second sample and hold circuits simultaneously through a single output channel.

公开(公告)号：US20160078834A1

公开(公告)日：2016-03-17

申请号：US14857411

申请日：2015-09-17

Applicant: LG DISPLAY CO., LTD.

Inventor： Seokhyun HONG ,  Chulwon LEE ,  Juyoung NOH ,  Osung DO

IPC: G09G3/36 ,  G11C19/00 ,  G09G3/32

CPC classification number: G11C19/00 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3674 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/287

Abstract: A gate driving circuit and a display device using the same are discussed. The gate driving circuit according to an embodiment includes a first shift register configured to sequentially shift a gate start pulse in response to a gate shift clock and output a gate pulse shifted on a per block basis, each block including a plurality of gate lines, a second shift register configured to sequentially shift the gate start pulse in response to the gate shift clock and output a gate pulse shifted on a per gate line basis, and a controller configured to supply the gate shift clock to one of the first and second shift registers.

Abstract translation: 讨论了栅极驱动电路和使用其的显示装置。 根据实施例的栅极驱动电路包括第一移位寄存器，其被配置为响应于栅极移位时钟顺序移位栅极起始脉冲，并输出以每个块为基准移位的栅极脉冲，每个块包括多个栅极线， 第二移位寄存器，其被配置为响应于所述栅极移位时钟顺序移位所述栅极起始脉冲，并输出在每个栅极线上移位的栅极脉冲，以及控制器，被配置为将所述栅极移位时钟提供给所述第一和第二移位寄存器 。