Abstract:
A display panel includes a first pixel area in which a plurality of light emitting elements and a plurality of pixel circuit are disposed, and a second pixel area in which a plurality of light emitting elements are disposed, and the second pixel area further may include a plurality of transparent extension lines configured to electrically connect the plurality of light emitting elements disposed in the second pixel area to the plurality of pixel circuits disposed in the first pixel area.
Abstract:
A subpixel circuit and a display device including the subpixel circuit are discussed. The subpixel circuit in one example includes a light emitting element configured to receive a high-potential driving voltage at an anode electrode, and a driving transistor including a first node, a second node, and a third node. The subpixel circuit further includes a scan transistor controlled by a first scan signal and transmitting a data voltage through a data line, a storage capacitor, and a control circuit configured to control operations of the driving transistor, the scan transistor, and the storage capacitor. The control circuit can be located between a cathode electrode of the light emitting element and a low-potential base voltage line.
Abstract:
Embodiments disclose a display device including a display panel including a first display region having a plurality of first pixels, and a second display region having a plurality of second pixels and a plurality of light-transmitting regions, a plurality of data lines through which data signals of the plurality of first pixels and the plurality of second pixels are output, a plurality of gate lines through which gate signals of the plurality of first pixels and the plurality of second pixels are output, and a gate driving unit including a plurality of stages configured to output the gate signals to the plurality of gate lines and a dummy stage connected in parallel to at least one of the plurality of stages.
Abstract:
An LCD device can include a liquid crystal display panel having a plurality of gate lines; a controller configured to generate at least four clock signals with different phases; a first gate driver configured to apply a high gate voltage to odd-numbered gate lines in response to at least two of the clock signals; a second gate driver configured to apply the high gate voltage to even-numbered gate lines in response to other clock signals; primary discharge circuits each configured to apply a low gate voltage to the respective odd-numbered gate line in response to a carry signal opposite to a voltage level on one of posterior odd-and-even-numbered gate lines; and secondary discharge circuits each configured to apply the low gate voltage to the respective even-numbered gate line in response to the carry signal opposite to the voltage level on the other one of the posterior odd-and-even-numbered gate lines.
Abstract:
A display device can include a first display region including a plurality of first pixels, a second display region including a plurality of second pixels, and a boundary region disposed between the first display region and the second display region. The boundary region includes the plurality of first pixels and the plurality of second pixels. Also, the plurality of first pixels respectively include a plurality of first pixel circuits, the plurality of second pixels respectively include a plurality of second pixel circuits, and a transmittance of each of the plurality of second pixel circuits is higher than a transmittance of each of the plurality of first pixel circuits.
Abstract:
A display device and a mobile terminal including the same includes a display area in which a first group of display pixels to which pixel data is written are arranged, and a sensing area in which a second group of display pixels and a plurality of sensor pixels are arranged; each of the display pixels includes a pixel circuit configured to drive a light emitting element; each of the sensor pixels includes a photosensor driving circuit configured to drive a photodiode; a low potential power voltage and a pixel driving voltage are applied to the pixel circuit and the photosensor driving circuit; a cathode electrode of the light emitting element and the cathode electrode of the photodiode share the same metal electrode, and are commonly connected to a low potential power line to which the low potential power voltage is applied.
Abstract:
An LCD panel being driven in an overlapping drive mode by applying a gate high voltage during n horizontal synchronous intervals is disclosed. The LCD panel includes: a plurality of gate lines; and a gate driver configured to include a plurality of stages connected to the plurality of gate lines. The plurality of stages are grouped in a plurality of stage groups each including n stages. Odd-numbered stage groups each allows the n stages to be arranged in a Z shape with having a display area therebetween. Even-number stage groups each allows the n states to be arranged in an inverse-Z shape with having the display area therebetween.
Abstract:
An LCD device according to an embodiment includes a liquid crystal display panel in which n gate lines are formed; a timing controller to generate first to sixth clock signals; a first gate driver to apply a high gate voltage to one ends of the (2k−1)th gate lines in response to the first, third and fifth clock signals; a second gate driver to apply the high gate voltage to one ends of the (2k)th gate lines in response to the second, fourth and sixth clock signals; left discharge circuits each to apply a low gate voltage to the other end of the (2k−1)th gate line according to a voltage level on (2k+1)th gate line; and right discharge circuits each to apply the low gate voltage to the other end of the (2k)th gate line according to the voltage level on (2k+2)th gate line.