Abstract:
A display device may include a display panel including a plurality of pixels; and a data driver circuit configured to supply a data signal to the plurality of the pixels through data lines. A gate driver circuit, configured to supply a gate signal to the plurality of the pixels through gate lines, is disposed in the display panel. The display panel includes a driving layer including a gate area having the gate driver circuit; and a pixel circuit layer including an active area having a pixel area in which each of the plurality of pixels is disposed and a non-active area around the active area. The pixel circuit layer includes a light emitting diode, a clock line configured to supply a clock signal to the gate driver circuit, and a shielding pattern between the light emitting diode and the clock line.
Abstract:
A display device can include a plurality of sub pixels disposed on a substrate; a first driver disposed in each of the plurality of sub pixels, the first driver being configured to generate a first driving current for a normal mode in which an image is displayed in a luminance range equal to or lower than a predetermined luminance; a second driver disposed in each of the plurality of sub pixels, the second driver being configured to generate a second driving current for a high luminance mode in which the luminance range is higher than the predetermined luminance; and a light emitting diode. Also, the light emitting diode is configured to receive the first driving current in the normal mode, and receive a sum of the first driving current and the second driving current in the high luminance mode.
Abstract:
Disclosed are a shift register and a flat panel display device. The shift register includes a plurality of stages that supply a gate-on voltage pulse to a plurality of gate lines formed in a display panel. Each of the stages includes a pull-up transistor configured to supply one of a plurality of clock signals to an output node according to a voltage of a first node, a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node, a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal, and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines using the clock signal.
Abstract:
An organic light emitting display device includes a TFT substrate on which a display area is defined, a thin film encapsulation layer disposed on the TFT substrate such that the thin film encapsulation layer covers the display area, and a bottom pad disposed on the lower surface of the TFT substrate, and is configured to displays an image; a flexible printed circuit board mounted on the bottom pad of the panel assembly; and a connection line that is disposed on at least one of the upper, lower, left side, and right side surfaces of the TFT substrate, and interconnects an upper signal line disposed on the top surface of the TFT substrate and the bottom pad disposed on the lower surface of the TFT substrate.
Abstract:
A display device in one example includes a display panel having pixels on a substrate being divided into a first area at a center area and a second area adjacent to the first area. The display panel further includes a gate driver having stages configured to supply a gate signal to the pixels through gate lines. Each of the stages included in the gate driver is disposed in a gate area that at least partially overlaps the first area and the second area. The pixels include first pixels disposed on the first area and second pixels disposed on the second area. Further, the first pixels can be disposed in the first area at a first density and the second pixels can be disposed in the second area at a second pixel density being lower than the first pixel density.