公开(公告)号：US10699645B2

公开(公告)日：2020-06-30

申请号：US15845829

申请日：2017-12-18

Applicant: LG Display Co., Ltd.

Inventor： JunHo Bong ,  WooSung Shim

IPC: G09G3/3266 ,  G09G3/3233 ,  G09G3/20 ,  G11C19/28 ,  G09G5/00 ,  G09G5/10

Abstract: Disclosed herein is a gate driver including a plurality of stages. The nth stage of the plurality of stages includes a first scan signal output unit configured to output the kth clock as a first scan signal through a first scan signal output node when a voltage of a Q-node is at a high state, and an emission control signal output unit configured to output a gate high voltage through an emission control signal output node when a voltage of the first scan signal output node and a voltage of an EQ-node are at the high state by an emission control clock. The emission control signal output unit is electrically connected to the Q-node. The gate driver includes a scan signal output and an emission control signal output, so that GIPs having the same configuration can be disposed on the left and right sides of a display panel.

公开(公告)号：US10198987B2

公开(公告)日：2019-02-05

申请号：US15840927

申请日：2017-12-13

Applicant: LG DISPLAY CO., LTD.

Inventor： WooSung Shim ,  JunHo Bong

IPC: G09G3/20 ,  G11C19/28 ,  G11C19/18 ,  H03K17/56

Abstract: The gate driving circuit includes a shift register including a plurality of stages. An n-th stage among the plurality of stages includes: a pull-up switching element outputting a first clock to an output node in accordance with a voltage in a Q node, a pull-down switching element outputting a gate low voltage VGL to the output node in accordance with a voltage in a QB node, and a logic unit inverting and outputting a voltage in the Q node and a voltage in the QB node. The logic unit includes a first switching element including a gate to which a fourth clock is input and being between a start voltage line which supplies a start voltage and the Q node, a second switching element including a gate connected to the Q node and being connected to the QB node, a third switching element being between the second switching element and a gate low voltage line which supplies the gate low voltage, a fourth switching element including a gate to which a third clock is input and being between a gate high voltage line which supplies a gate high voltage and the QB node, a fifth switching element including a gate connected to the QB node and being between the Q node and the gate low voltage line, a first capacitor between the Q node and the output node, and a second capacitor between the gate low voltage line and the gate of the pull-down switching element.