Abstract:
A display device for low speed drive includes a display panel including gate lines, data lines, and pixels respectively formed at crossings of the gate lines and the data lines, a source driver supplying data voltages to the data lines, a gate driver supplying a gate pulse to the gate lines, and a timing controller which time-divides one frame into n sub-frames, where n is a positive integer equal to or greater than 2, groups the gate lines into n gate groups, controls an operation of the gate driver in each of the n sub-frames to complete a scan operation of a corresponding gate group during a scan period of each of the n sub-frames, generates a buffer operation control signal, and cuts off a driving power source applied to buffers of the source driver during a skip period excluding the scan period from each of the n sub-frames.