公开(公告)号：US11837171B2

公开(公告)日：2023-12-05

申请号：US17531398

申请日：2021-11-19

Applicant: LG Display Co., Ltd.

Inventor： Sunghak Jo ,  Taehee Ko

IPC: G09G3/32 ,  G09G3/3266 ,  H10K59/38 ,  H10K59/88

CPC classification number: G09G3/3266 ,  H10K59/38 ,  H10K59/88 ,  G09G2300/0842 ,  G09G2310/08 ,  G09G2320/0219

Abstract: A gate driver includes: circuit parts having circuit elements thereon. The circuit parts are spaced apart from each other. Transparent parts are between the circuit parts. External light may pass through the transparent parts. Each of the circuit parts may include at least one circuit block. Each of the circuit blocks may be configured to perform the same function as others of the circuit blocks.

公开(公告)号：US11783780B2

公开(公告)日：2023-10-10

申请号：US17559982

申请日：2021-12-22

Applicant: LG Display Co., Ltd.

Inventor： Sunghak Jo ,  Seongku Lee

IPC: G09G3/32 ,  G09G3/3266 ,  G09G3/3258 ,  G09G3/3208

CPC classification number: G09G3/3266 ,  G09G3/32 ,  G09G3/3208 ,  G09G3/3258 ,  G09G2310/021 ,  G09G2310/0264 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2330/00 ,  G09G2330/02 ,  G09G2330/12

Abstract: Proposed is a gate driver and a display device having the same. The gate driver includes a plurality of stage circuits, wherein each of the plurality of stage circuits includes a shift register configured to control charging and discharging of a Q node and a QB node, and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers includes a first transistor configured to transmit a voltage of the Q node to a Q′ node, a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node, and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.

公开(公告)号：US20220208114A1

公开(公告)日：2022-06-30

申请号：US17559982

申请日：2021-12-22

Applicant: LG Display Co., Ltd.

Inventor： Sunghak Jo ,  Seongku Lee

IPC: G09G3/3266

Abstract: Proposed is a gate driver and a display device having the same. The gate driver includes a plurality of stage circuits, wherein each of the plurality of stage circuits includes a shift register configured to control charging and discharging of a Q node and a QB node, and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers includes a first transistor configured to transmit a voltage of the Q node to a Q′ node, a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node, and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.

公开(公告)号：US20240203359A1

公开(公告)日：2024-06-20

申请号：US18538685

申请日：2023-12-13

Applicant: LG Display Co., Ltd.

Inventor： Sunghak Jo

IPC: G09G3/3266 ,  G09G3/36

CPC classification number: G09G3/3266 ,  G09G3/3677 ,  G09G2310/063 ,  G09G2310/08

Abstract: A gate driving circuit that prevents the discharge of the Q node due to the leakage current in the last stage when the panel is cut, thereby preventing distortion of the gate signal, and a display including the same is disclosed. The gate driving circuit includes a plurality of stages driving a plurality of gate lines, and each of the plurality of stages includes a pull-up transistor pull-up driving an output terminal in response to a signal of a Q node of a N stage; a pull-down transistor pull-down driving an output terminal in response to a signal of a Qb node of the N stage; and a first transistor coupled between a source electrode of the pull-down transistor and a Q node of a N−1 stage, and pull-down driving the Q node of the N−1 stage in response to a signal of the output terminal of the N stage.

公开(公告)号：US11854467B2

公开(公告)日：2023-12-26

申请号：US17529053

申请日：2021-11-17

Applicant: LG Display Co., Ltd.

Inventor： Sunghak Jo ,  Binn Kim

IPC: G11C19/28 ,  G09G3/32 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3275

CPC classification number: G09G3/32 ,  G11C19/28 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G2230/00 ,  G09G2300/04 ,  G09G2300/0413 ,  G09G2310/0205 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2320/0295

Abstract: A gate driver and a display device including the gate driver are discussed. The gate driver in one example includes a shift register configured to control charging and discharging of a Q node and a QB node, and i output buffers sequentially connected to the shift register, where i is a natural number of at least 2. Each output buffer is configured to output a gate signal to a corresponding gate line in response to a voltage of the Q node and a voltage of the QB node. The gate driver further includes a dummy output buffer connected to the last stage of the shift register and configured to output a dummy signal to a dummy line in response to the voltage of the Q node.