公开(公告)号：US20230315666A1

公开(公告)日：2023-10-05

申请号：US17754528

申请日：2019-10-10

Applicant: LG ELECTRONICS INC.

Inventor： Hyoung Kyu CHOI ,  Jin Kyoung KIM

IPC: G06F13/40 ,  G06F9/4401

CPC classification number: G06F13/4068 ,  G06F9/4411

Abstract: Disclosed is an electronic device including a first interface configured to receive information about a device information storage device configured to store information about another electronic device, a second interface configured to communicate with a processor of the other electronic device, and at least one processor, wherein the at least one processor is configured to, when the device information storage device is identified through the first interface, acquire the information about the other electronic device from the device information storage device through the first interface, when the device information storage device is not identified through the first interface, check whether the other electronic device is identified through the second interface, and when the other electronic device is identified through the second interface, acquire the information about the other electronic device through the second interface based on communication with the processor of the other electronic device.

公开(公告)号：US20210129779A1

公开(公告)日：2021-05-06

申请号：US16786862

申请日：2020-02-10

Applicant: LG ELECTRONICS INC.

Inventor： Jin Kyoung KIM ,  Hyoungkyu CHOI ,  Hyung Bin PARK ,  Ilgyeong HONG

IPC: B60R16/033 ,  G05B19/042

Abstract: Disclosed are an apparatus and method for managing power of a multi SoC module in a vehicle. The apparatus for managing power of a multi SoC module in a vehicle includes a multi SoC module configured to include a plurality of SoCs, and a processor configured to change the module mode of the multi SoC module from a normal module mode to a half low power module mode in response to a capacity of a main battery in a vehicle in a driving state being lower than a set first reference value, and maintain a first SoC associated with safety among the plurality of SoCs supplied with power from the main battery in a normal mode while switching a remaining second SoC other than the first SoC to a low power mode.