公开(公告)号：US20040253840A1

公开(公告)日：2004-12-16

申请号：US10847287

申请日：2004-05-18

Applicant: LG.PHILIPS LCD CO., LTD.

Inventor： JaeSung You

IPC: H01L021/76 ,  H01L021/26 ,  H01L021/20

CPC classification number: H01L21/0268 ,  H01L21/02532 ,  H01L21/2026 ,  H01L21/268

Abstract: A method of crystallizing silicon including preparing a substrate having an amorphous silicon film formed thereon, aligning a mask having a first energy region and a second energy region over a first region of the amorphous silicon film formed on the substrate, irradiating a laser beam through the first and second energy regions of the mask onto the first region of the amorphous silicon film, crystallizing the first region of the amorphous silicon film by irradiating the laser beam through the first energy region of the mask, and activating the crystallized first region by irradiating the laser beam through the second energy region.

Abstract translation: 一种使硅结晶的方法，包括制备其上形成有非晶硅膜的衬底，在形成在衬底上的非晶硅膜的第一区域上对准具有第一能量区和第二能区的掩模，照射激光束通过 将掩模的第一和第二能量区域放置在非晶硅膜的第一区域上，通过照射穿过掩模的第一能量区域的激光束使非晶硅膜的第一区域结晶，并通过照射 激光束通过第二能量区。

公开(公告)号：US20040266082A1

公开(公告)日：2004-12-30

申请号：US10843569

申请日：2004-05-12

Applicant: LG.Philips LCD Co., Ltd.

Inventor： JaeSung You

IPC: H01L021/336

CPC classification number: H01L29/66765 ,  H01L27/1285 ,  H01L29/78678

Abstract: A method of forming a thin film transistor includes forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an amorphous silicon layer on the gate insulating layer, crystallizing the amorphous silicon layer within an active region corresponding to the gate electrode to form a polycrystalline silicon layer, etching the amorphous silicon layer such that an etch rate of amorphous silicon is greater than an etch rate of polycrystalline silicon to form a semiconductor layer of polycrystalline silicon in the active region, and forming source and drain electrodes on the semiconductor layer.

Abstract translation: 一种形成薄膜晶体管的方法包括：在衬底上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成非晶硅层，使非晶硅层在对应于 栅电极以形成多晶硅层，蚀刻非晶硅层，使得非晶硅的蚀刻速率大于多晶硅的蚀刻速率，以在有源区中形成多晶硅的半导体层，并形成源极和漏极 在半导体层上。