公开(公告)号：US20040222421A1

公开(公告)日：2004-11-11

申请号：US10833185

申请日：2004-04-28

Applicant: LG.Philips LCD Co., Ltd.

Inventor： Kyoung Mook Lee ,  Seung Hee Nam ,  Jae Young OH

IPC: H01L029/76

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F2001/136236 ,  H01L27/1288 ,  H01L29/66765

Abstract: A thin film transistor array substrate includes a gate line formed on a substrate, a data line formed on the substrate intersecting with the gate line to define a pixel region, a thin film transistor formed at the intersection of the gate line and the data line, the thin film transistor including gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode and the substrate, a semiconductor layer formed on the gate insulating layer, an ohmic contact layer on the semiconductor layer, and a source electrode and a drain electrode on the ohmic contact layer, and a transparent electrode material within the pixel region and connected to the drain electrode of the thin film transistor, wherein the gate insulating layer includes a gate insulating pattern underlying the data line and the transparent electrode material, and covering the gate line.

Abstract translation: 薄膜晶体管阵列基板包括形成在基板上的栅极线，形成在与栅极线交叉以限定像素区域的基板上的数据线，形成在栅极线和数据线的交叉处的薄膜晶体管， 所述薄膜晶体管包括形成在所述基板上的栅极电极，形成在所述栅极电极和所述基板上的栅极绝缘层，形成在所述栅极绝缘层上的半导体层，所述半导体层上的欧姆接触层以及源电极和 漏极电极和像素区域内的透明电极材料，并连接到薄膜晶体管的漏电极，其中栅极绝缘层包括位于数据线下方的栅绝缘图案和透明电极材料，以及 覆盖门线。