公开(公告)号：US10956346B1

公开(公告)日：2021-03-23

申请号：US15857756

申请日：2017-12-29

申请人： Lightbits Labs Ltd.

发明人： Shmuel Ben-Yehuda ,  Ofir Efrati ,  Sagi Grimberg ,  Eran Kirzner ,  Ziv Tishel ,  Fabian Trumper

IPC分类号： G06F13/28 ,  G06F13/16 ,  G06F3/06

摘要： A storage system that includes an in-line hardware accelerator, a solid-state drive (SSD) unit, a central processing unit (CPU), a volatile memory module, and an accelerator memory module that is coupled to the in-line hardware accelerator or belongs to the in-line hardware accelerator; wherein the in-line hardware accelerator is directly coupled to the SSD unit, the volatile memory and the non-volatile memory; wherein the CPU is directly coupled to the volatile memory and to the non-volatile memory; wherein the in-line hardware accelerator is configured to manage access to the SSD unit; wherein the in-line accelerator is configured to retrieve data stored in the volatile memory module and the non-volatile memory module without involving the CPU.

公开(公告)号：US11256431B1

公开(公告)日：2022-02-22

申请号：US15857761

申请日：2017-12-29

申请人： Lightbits Labs Ltd.

发明人： Shmuel Ben-Yehuda ,  Ofir Efrati ,  Sagi Grimberg ,  Eran Kirzner ,  Ziv Tishel ,  Fabian Trumper

IPC分类号： G06F3/06

摘要： A field programmable gate array (FPGA), that includes a trusted FPGA logic, an untrusted FPGA logic and a monitor; wherein the monitor is configured to monitor the untrusted FPGA logic and prevent the untrusted FPGA logic from violating predefined constrains imposed on an operation of the untrusted FPGA logic; wherein the predefined constraints are stored in a memory region of the FPGA that is not accessible to the untrusted FPGA logic.

公开(公告)号：US10990447B1

公开(公告)日：2021-04-27

申请号：US16033326

申请日：2018-07-12

申请人： LIGHTBITS LABS LTD.

发明人： Alexander Shpiner ,  Abel Alkon Gordon ,  Sagi Grimberg

IPC分类号： G06F15/16 ,  G06F9/50 ,  H04L29/08 ,  H04L12/911 ,  H04L12/925 ,  H04L12/927 ,  H04L29/06

摘要： A method and a system for controlling the access of a plurality of client computers to storage media, the system including: a processor, a Random-Access Memory (RAM) device; and a Network Interface Controller (NIC), configured to establish a plurality of connections with the clients. The processor may dynamically allocate a buffer memory space to each connected client computer on the RAM device, and the NIC may be configured to receive at least one storage access request from at least one client, over at least one computer network connection. The RAM device may accumulate data of the at least one storage access request in the buffer allocated to the respective connected client computer, and the processor may be configured, upon completion of the accumulation of data, to propagate the buffered data to at least one storage device of the storage media.

公开(公告)号：US10713162B1

公开(公告)日：2020-07-14

申请号：US15963131

申请日：2018-04-26

申请人： LIGHTBITS LABS LTD.

发明人： Shmuel Ben-Yehuda ,  Ofir Efrati ,  Roy Geron ,  Abel Alkon Gordon ,  Sagi Grimberg ,  Eran Kirzner ,  Ziv Tishel ,  Maor Vanmak ,  Ofer Hayut

IPC分类号： G06F12/02 ,  G06F12/10

摘要： A method and a system for accelerating computer data garbage collection (GC) on a non-volatile memory (NVM) computer storage device may include: monitoring, by a processor, a data validity parameter of at least one physical write unit (PWU), where the PWU may include a plurality of physical data pages of the NVM device; sending at least one GC command from the processor to an accelerator associated with the NVM device, based on the monitored data validity parameter; copying, by the accelerator, a plurality of data-objects stored on at least one first PWU, to a read address space comprised within the accelerator; copying valid data-objects from the read address space to a write address space comprised within the accelerator until the amount of data in the write address space exceeds a predefined threshold; and storing, by the accelerator, the data content in at least one second PWU in the NVM media.

公开(公告)号：US10684964B1

公开(公告)日：2020-06-16

申请号：US16051500

申请日：2018-08-01

申请人： LIGHTBITS LABS LTD.

发明人： Abel Alkon Gordon ,  Sagi Grimberg ,  Shmuel Ben-Yehuda

IPC分类号： G06F13/16 ,  G06F13/18 ,  G06F12/02 ,  G06F3/06

摘要： A system and a method for reducing read latency of a storage media associated with at least one host computer, by at least one processor, may include assigning each storage segment of the non-volatile storage to a first Read-Latency Set (RLS) and a second RLS, wherein the first RLS is attributed a read/write mode and the second RLS is attributed a read-only mode; receiving read-requests and write-requests from the at least one host computer, wherein each of said requests is attributed a priority; and serving the received requests according to RLS work modes and according to the priority of each request.