Abstract:
A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.
Abstract:
Improved threshold adaptation is provided for a predefined pattern in data. A detection threshold employed by a Euclidean detector to detect a pattern (such as a Servo Address Mark) in data is adapted by determining a minimum Euclidean distance metric Dp before the pattern is declared in a given portion of the data; determining a Euclidean distance metric Ds at a time when the pattern is found in the given portion, wherein at least one of the patterns is found using a Hamming detector; determining, for a plurality of the portions, a minimum Dp value, Dpmin, that is a substantial minimum Dp value for the plurality of portions and a maximum Ds value, Dsmax, that is a substantial maximum Ds value for the plurality of portions; and determining the detection threshold based on the minimum Dp value, Dpmin, and the maximum Ds value, Dsmax. The detection threshold is optionally based on a configurable margin gain value.
Abstract:
A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.
Abstract:
The disclosure is directed to a system and method for accessing one or more values of a lookup table. In some embodiments, one or more read only memory devices are configured for storing a first plurality of values of the lookup table, and one or more combinational logic circuits are configured for accessing a second plurality of values of the lookup table. At least one of hardware area and timing pressures are mitigated through various storage and access schemes.