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公开(公告)号:US20170259836A1
公开(公告)日:2017-09-14
申请号:US15351503
申请日:2016-11-15
申请人: LSIS CO., LTD.
发明人: Yong-Gee CHO , Dong-Han WOO , Yung BANG
IPC分类号: B61L7/10 , B61L29/02 , B61L27/00 , G05B19/042
摘要: The present disclosure relates to a CPU module for processing railway signals, and more specifically to a CPU module for processing railway signals that controls operation timing of a first comparator, a signal processing unit and a second comparator.