公开(公告)号：US06903013B2

公开(公告)日：2005-06-07

申请号：US10439923

申请日：2003-05-16

申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Yong Ju ,  Jia Zhen Zheng

发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Yong Ju ,  Jia Zhen Zheng

IPC分类号： H01L21/285 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/5227 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved method to deposit, by atomic layer deposition, ALD, a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a damascene process, for the fabrication of interconnects and inductors, has been developed. A process flow outlining the method of the present invention is as follows: (1) formation of trenches and channels, (2) atomic layer deposition of copper barrier and seed, (3) electroless deposition of copper, (4) chemical mechanical polishing back of excess copper, and (5) barrier deposition, SiN, forming copper interconnects and inductors.

摘要翻译： 已经开发了一种改进的方法，通过原子层沉积，ALD，用于化学镀铜的铜屏障和种子层，在镶嵌工艺中的填充沟槽和沟道或隧道开口，用于制造互连和电感器。 概述本发明方法的工艺流程如下：（1）形成沟槽和通道，（2）铜屏障和晶种的原子层沉积，（3）铜的无电沉积，（4）化学机械抛光 的过量铜，和（5）阻挡层沉积，SiN，形成铜互连和电感器。

公开(公告)号：US06284594B1

公开(公告)日：2001-09-04

申请号：US09580607

申请日：2000-05-30

申请人： Yong Ju ,  Kai Shao ,  Yimin Wang ,  Shao-Fu Sanford Chu

发明人： Yong Ju ,  Kai Shao ,  Yimin Wang ,  Shao-Fu Sanford Chu

IPC分类号： H01L218242

CPC分类号： H01L27/0629 ,  H01L21/3144 ,  H01L28/40

摘要： A process for simultaneously forming a polysilicon gate structure, for a transfer gate transistor, and a polysilicon top plate, for a capacitor structure, on an underlying planar surface, has been developed. The process features the formation of a polysilicon bottom plate, for the capacitor structure, embedded in a first opening in composite insulator layer, and the formation of an active device region, for a transfer gate transistor structure, via the selective growth of an epitaxial silicon layer, in a second opening of the composite insulator layer, resulting in a planar top surface topography. The presence of this topography reduces the risk of residual polysilicon, present after patterning of the polysilicon gate structure, and of the capacitor, polysilicon top plate.

摘要翻译： 已经开发了用于在底层平面上形成用于电容器结构的传输栅极晶体管和多晶硅顶板的多晶硅栅极结构的工艺。 该方法的特征在于形成多晶硅底板，用于电容器结构，嵌入在复合绝缘体层中的第一开口中，并且通过外延硅的选择性生长形成用于传输栅晶体管结构的有源器件区 层，在复合绝缘体层的第二开口中，产生平坦的顶表面形貌。 这种形貌的存在降低了在多晶硅栅极结构图案化之后存在的残余多晶硅以及电容器，多晶硅顶板的风险。

公开(公告)号：US06828635B2

公开(公告)日：2004-12-07

申请号：US10655475

申请日：2003-09-04

申请人： Shesh Mani Panday ,  Alan Shafi ,  Yong Ju

发明人： Shesh Mani Panday ,  Alan Shafi ,  Yong Ju

IPC分类号： H01L2976

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/7322

摘要： An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.

摘要翻译： 实现了可与CMOS FET处理集成的改进的NPN双极晶体管。 晶体管使用CMOS工艺和一个额外的掩模和注入步骤在衬底上形成。 使用CMOS N阱形成集电极触点（达到），P阱用于形成基极。 在N个阱，P个阱和浅沟槽隔离区之下形成N个掺杂的第三阱，以提供子集电极。 由于P阱不通过STI注入，所以基极宽度减小，电流增益增加。 在基极上形成的栅电极掩模元件分离发射极和基极接触区域，改善发射极对基极击穿电压。 然后，CMOS源极/漏极N型注入器在发射极区域中形成发射极，并在集电极触点中形成欧姆接触。 源极/漏极P型注入器形成欧姆基极触点以完成双极晶体管。

公开(公告)号：US20070064689A1

公开(公告)日：2007-03-22

申请号：US10572085

申请日：2004-09-16

申请人： Yong Shin ,  Seok Song ,  Yong Shin ,  Yong Ju

发明人： Yong Shin ,  Seok Song ,  Yong Shin ,  Yong Ju

IPC分类号： H04L12/56

CPC分类号： H04L29/12028 ,  H04L61/103

摘要： Disclosed is a technology by which rules on communication permission or control are enforced to network internal devices such that an environment which looks as if to have a virtual firewall existing between network internal devices can be established. A communication control apparatus for this is located on the same level in the network as other devices are located. By using this communication control apparatus, an address resolution protocol (ARP) packet in which a data link layer address is manipulated is provided to devices that are the objects of communication cut-off, such that data packets transmitted by the communication cut-off object devices are transmitted to manipulated abnormal addresses. By doing so, communication with the communication cut-off object devices is cut off. For a device which is in a communication cut-off state although the device is not an object of communication cut-off any more, the communication control apparatus transmits an ARP packet including normal address information to the device such that the communication cut-off state is canceled.

摘要翻译： 公开了一种技术，通过该规则对通信许可或控制进行网络内部设备的执行，从而可以建立在网络内部设备之间存在虚拟防火墙的环境。 用于其的通信控制装置位于与其他设备所在的网络相同的级上。 通过使用该通信控制装置，将其中操作了数据链路层地址的地址解析协议（ARP）分组提供给作为通信切断对象的设备，使得由通信切断对象发送的数据分组 设备被传送到操纵的异常地址。 通过这样做，与通信中断对象设备的通信被切断。 对于处于通信切断状态的设备，尽管设备不再是通信中断的对象，但是通信控制设备向设备发送包括普通地址信息的ARP分组，使得通信中断状态 被取消。

公开(公告)号：US06630377B1

公开(公告)日：2003-10-07

申请号：US10246228

申请日：2002-09-18

申请人： Shesh Mani Panday ,  Alan Shafi ,  Yong Ju

发明人： Shesh Mani Panday ,  Alan Shafi ,  Yong Ju

IPC分类号： H01L218238

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/7322

摘要： An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.

摘要翻译： 实现了可与CMOS FET处理集成的改进的NPN双极晶体管。 晶体管使用CMOS工艺和一个额外的掩模和注入步骤在衬底上形成。 使用CMOS N阱形成集电极触点（达到），P阱用于形成基极。 在N个阱，P个阱和浅沟槽隔离区之下形成N个掺杂的第三阱，以提供子集电极。 由于P阱不通过STI注入，所以基极宽度减小，电流增益增加。 在基极上形成的栅电极掩模元件分离发射极和基极接触区域，改善发射极对基极击穿电压。 然后，CMOS源极/漏极N型注入器在发射极区域中形成发射极，并在集电极触点中形成欧姆接触。 源极/漏极P型注入器形成欧姆基极触点以完成双极晶体管。