公开(公告)号：US20070139228A1

公开(公告)日：2007-06-21

申请号：US11538336

申请日：2006-10-03

申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

IPC分类号： H03M7/00

CPC分类号： H03M7/40

摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

摘要翻译： 用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。 系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。 有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。 此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。

公开(公告)号：US07132963B2

公开(公告)日：2006-11-07

申请号：US11046048

申请日：2005-01-28

申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

摘要翻译： 用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。 系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。 有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。 此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。

公开(公告)号：US07804430B2

公开(公告)日：2010-09-28

申请号：US12133489

申请日：2008-06-05

申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

摘要翻译： 用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。 系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。 有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。 此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。

公开(公告)号：US20060071829A1

公开(公告)日：2006-04-06

申请号：US11046048

申请日：2005-01-28

申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

公开(公告)号：US20060047937A1

公开(公告)日：2006-03-02

申请号：US10929992

申请日：2004-08-30

申请人： Richard Selvaggi ,  Larry Pearlstein

发明人： Richard Selvaggi ,  Larry Pearlstein

IPC分类号： G06F12/08

CPC分类号： G06F9/345 ,  G06F9/30101 ,  G06F9/3555

摘要： A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

公开(公告)号：US20060095712A1

公开(公告)日：2006-05-04

申请号：US10940150

申请日：2004-09-13

申请人： Richard Selvaggi ,  Larry Pearlstein

发明人： Richard Selvaggi ,  Larry Pearlstein

IPC分类号： G06F15/00

CPC分类号： G06F9/30014 ,  G06F7/509 ,  G06F7/544 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/3885 ,  G06F2207/3828

摘要： A SIMD processor includes an ALU having data interconnects facilitating the concurrent processing of overlapping data portions of at least one operand store. Such interconnects facilitate the calculation of shift-invariant convolutions, and sum of absolute differences between an operand in the operand store and another operand.

公开(公告)号：US20060059484A1

公开(公告)日：2006-03-16

申请号：US10939804

申请日：2004-09-13

申请人： Richard Selvaggi ,  Larry Pearlstein

发明人： Richard Selvaggi ,  Larry Pearlstein

IPC分类号： G06F9/46

CPC分类号： G06F9/4843 ,  G06F9/544

摘要： In a multiprocessor system, a task control processor may be placed in the path connecting each execution processor to a system bus. Such task control processors may detect the completion of a first task on an associated execution processor and, responsively, generate commands to lead to the initiation of a second task on the same, or another, execution processor. Such task completion detection and task initiation by the task control processors removes, from a central processor or the execution processors, the burden of performing such tasks, thereby improving the efficiency of the entire system.

摘要翻译： 在多处理器系统中，可以将任务控制处理器放置在将每个执行处理器连接到系统总线的路径中。 这样的任务控制处理器可以检测相关联的执行处理器上的第一任务的完成，并且响应地产生命令以导致在同一个或另一个执行处理器上启动第二个任务。 任务控制处理器的这种任务完成检测和任务启动从中央处理器或执行处理器移除执行这些任务的负担，从而提高整个系统的效率。

公开(公告)号：US20060095739A1

公开(公告)日：2006-05-04

申请号：US10940123

申请日：2004-09-13

申请人： Richard Selvaggi ,  Larry Pearlstein

发明人： Richard Selvaggi ,  Larry Pearlstein

IPC分类号： G06F9/44

CPC分类号： G06F9/30036 ,  G06F9/30021

摘要： A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output at a corresponding location. A further single instruction executable by the SIMD processor, may be applied to results obtained using such a single min/max instruction, to allow such instructions to operate on two dimensional arrays.

公开(公告)号：US20060033757A1

公开(公告)日：2006-02-16

申请号：US11250754

申请日：2005-10-14

申请人： Richard Selvaggi ,  Gary Root

发明人： Richard Selvaggi ,  Gary Root

IPC分类号： G09G5/00

CPC分类号： G06T15/005

摘要： A method for processing video image data including a plurality of different image data types begins by providing tasks to be performed on each different image data type. The image data is divided into a plurality of groups based on the image data type. A set of arithmetic operations required to accomplish the tasks provided for the corresponding image data type is determined. Each arithmetic operation is assigned to one of a plurality of commonly used arithmetic units which performs the arithmetic operation, whereby each image data type is transformed in accordance with the corresponding provided tasks. The transformed image data of each group is combined, completing the processing.

摘要翻译： 一种用于处理包括多个不同图像数据类型的视频图像数据的方法是通过提供对每个不同图像数据类型执行的任务而开始的。 基于图像数据类型将图像数据分成多个组。 确定完成为相应图像数据类型提供的任务所需的一组算术运算。 每个算术运算被分配给执行算术运算的多个常用的算术单元中的一个，由此根据相应的提供的任务来转换每个图像数据类型。 组合每组的变换图像数据，完成处理。