公开(公告)号：US20070139228A1

公开(公告)日：2007-06-21

申请号：US11538336

申请日：2006-10-03

申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

IPC分类号： H03M7/00

CPC分类号： H03M7/40

摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

摘要翻译： 用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。 系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。 有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。 此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。

公开(公告)号：US07132963B2

公开(公告)日：2006-11-07

申请号：US11046048

申请日：2005-01-28

申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

摘要翻译： 用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。 系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。 有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。 此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。

公开(公告)号：US07804430B2

公开(公告)日：2010-09-28

申请号：US12133489

申请日：2008-06-05

申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

摘要翻译： 用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。 系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。 有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。 此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。

公开(公告)号：US20060071829A1

公开(公告)日：2006-04-06

申请号：US11046048

申请日：2005-01-28

申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

公开(公告)号：US20060095712A1

公开(公告)日：2006-05-04

申请号：US10940150

申请日：2004-09-13

申请人： Richard Selvaggi ,  Larry Pearlstein

发明人： Richard Selvaggi ,  Larry Pearlstein

IPC分类号： G06F15/00

CPC分类号： G06F9/30014 ,  G06F7/509 ,  G06F7/544 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/3885 ,  G06F2207/3828

摘要： A SIMD processor includes an ALU having data interconnects facilitating the concurrent processing of overlapping data portions of at least one operand store. Such interconnects facilitate the calculation of shift-invariant convolutions, and sum of absolute differences between an operand in the operand store and another operand.

公开(公告)号：US20060059484A1

公开(公告)日：2006-03-16

申请号：US10939804

申请日：2004-09-13

申请人： Richard Selvaggi ,  Larry Pearlstein

发明人： Richard Selvaggi ,  Larry Pearlstein

IPC分类号： G06F9/46

CPC分类号： G06F9/4843 ,  G06F9/544

摘要： In a multiprocessor system, a task control processor may be placed in the path connecting each execution processor to a system bus. Such task control processors may detect the completion of a first task on an associated execution processor and, responsively, generate commands to lead to the initiation of a second task on the same, or another, execution processor. Such task completion detection and task initiation by the task control processors removes, from a central processor or the execution processors, the burden of performing such tasks, thereby improving the efficiency of the entire system.

摘要翻译： 在多处理器系统中，可以将任务控制处理器放置在将每个执行处理器连接到系统总线的路径中。 这样的任务控制处理器可以检测相关联的执行处理器上的第一任务的完成，并且响应地产生命令以导致在同一个或另一个执行处理器上启动第二个任务。 任务控制处理器的这种任务完成检测和任务启动从中央处理器或执行处理器移除执行这些任务的负担，从而提高整个系统的效率。

公开(公告)号：US20060095739A1

公开(公告)日：2006-05-04

申请号：US10940123

申请日：2004-09-13

申请人： Richard Selvaggi ,  Larry Pearlstein

发明人： Richard Selvaggi ,  Larry Pearlstein

IPC分类号： G06F9/44

CPC分类号： G06F9/30036 ,  G06F9/30021

摘要： A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output at a corresponding location. A further single instruction executable by the SIMD processor, may be applied to results obtained using such a single min/max instruction, to allow such instructions to operate on two dimensional arrays.

公开(公告)号：US20060047937A1

公开(公告)日：2006-03-02

申请号：US10929992

申请日：2004-08-30

申请人： Richard Selvaggi ,  Larry Pearlstein

发明人： Richard Selvaggi ,  Larry Pearlstein

IPC分类号： G06F12/08

CPC分类号： G06F9/345 ,  G06F9/30101 ,  G06F9/3555

摘要： A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

公开(公告)号：US08760574B2

公开(公告)日：2014-06-24

申请号：US12433686

申请日：2009-04-30

申请人： Larry Pearlstein ,  Samir Hulyalkar

发明人： Larry Pearlstein ,  Samir Hulyalkar

IPC分类号： H04N7/01

CPC分类号： G06T3/4007 ,  G09G5/006 ,  G09G2340/0435 ,  H04N7/0132 ,  H04N7/0135

摘要： An image processing method for frame rate conversion, comprising: receiving a stream of input pictures at an input frame rate, at least some of the input pictures being new pictures, the new pictures appearing within the stream of input pictures at an underlying new picture rate; generating interpolated pictures from certain ones of the input pictures; outputting a stream of output pictures at an output frame rate, the stream of output pictures including a blend of the new pictures and the interpolated pictures, the interpolated pictures appearing in the stream of output pictures at an average interpolated picture rate; and causing a variation in the average interpolated picture rate in response to detection of a variation in the underlying new picture rate.

摘要翻译： 一种用于帧速率转换的图像处理方法，包括：以输入帧速率接收输入图像流，所述输入图像中的至少一些是新图像，所述新图像以基本新图像速率出现在所述输入图像流内 ; 从某些输入图像生成内插图像; 以输出帧速率输出输出图像流，输出图像流包括新图像和内插图像的混合，内插图像以平均内插图像速率出现在输出图像流中; 并且响应于底层新图像速率的变化的检测而导致平均内插图像速率的变化。

公开(公告)号：US07782938B2

公开(公告)日：2010-08-24

申请号：US10617605

申请日：2003-07-11

申请人： Larry Pearlstein

发明人： Larry Pearlstein

IPC分类号： H04B1/66

CPC分类号： H04N19/51 ,  H04N19/55 ,  H04N21/23892

摘要： Methods and apparatus for encoding image data to facilitate subsequent insertion of local image data. Also methods and apparatus for inserting image data, e.g., at local broadcast stations, without having to fully decode a received encoded bitstream. The encoding methods involve treating images to be encoded as a plurality of distinct, non-overlapping image regions or segments for encoding purposes. Image segments which are designated for use for local data insertion are not used as reference data for motion compensated prediction purposes when generating motion vectors to represent image areas, e.g., the area representing the main picture, which are outside the local data insertion segments. Because image segments which may be replaced are not used as reference data for image segments which will not be replaced, unintentional prediction errors which might otherwise result from replacing one or more image segments as part of a local data insertion operation are avoided.

摘要翻译： 用于编码图像数据以便于随后插入局部图像数据的方法和装置。 以及用于例如在本地广播站插入图像数据的方法和装置，而不必完全解码所接收的编码比特流。 编码方法涉及将图像编码为用于编码目的的多个不同的，不重叠的图像区域或片段。 指定用于本地数据插入的图像段在生成用于表示图像区域（例如，表示主图像的区域）的运动矢量时不用作用于运动补偿预测目的的参考数据，其在本地数据插入段之外。 由于可以替换的图像段不被用作不被替换的图像段的参考数据，因此避免了由于将一个或多个图像段替换为本地数据插入操作的一部分而导致的意外预测误差。