公开(公告)号：US07032148B2

公开(公告)日：2006-04-18

申请号：US10876784

申请日：2004-06-28

申请人： Laung-Terng (L.-T.) Wang ,  Shun-Miin (Sam) Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu

发明人： Laung-Terng (L.-T.) Wang ,  Shun-Miin (Sam) Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu

IPC分类号： G01R31/3177 ,  G01R31/3181 ,  G01R31/3185

CPC分类号： G01R31/318547 ,  G01R31/318536

摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.

摘要翻译： 一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获的扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。 基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。 该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入 。 还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。

公开(公告)号：US07124342B2

公开(公告)日：2006-10-17

申请号：US10850460

申请日：2004-05-21

申请人： Laung-Terng Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu ,  Shun-Miin (Sam) Wang

发明人： Laung-Terng Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu ,  Shun-Miin (Sam) Wang

IPC分类号： G06F11/00

CPC分类号： G01R31/318594 ,  G01R31/3008 ,  G01R31/318342 ,  G01R31/318364 ,  G01R31/318563

摘要： A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network. The method comprises compiling the scan-based integrated circuit into a sequential circuit model; specifying input constraints on the scan-based integrated circuit during a shift and capture operation; specifying a clock grouping to map the N clock domains into G clock domain groups, where N>G>1; transforming the sequential circuit model into an equivalent combinational circuit model according to the input constraints and the clock grouping; and generating the stimuli and test responses on the equivalent combinational circuit model according to the input constraints.

摘要翻译： 一种用于产生用于以选定的扫描测试模式或选定的自测模式测试基于扫描的集成电路中的故障的刺激和测试响应的方法，所述基于扫描的集成电路包含多个扫描链，N个时钟域， 和C个跨时钟域块，每个扫描链包括串联耦合的多个扫描单元，每个时钟域具有一个捕获时钟，每个交叉时钟域块包括组合逻辑网络。 该方法包括将基于扫描的集成电路编译成顺序电路模型; 在移位和捕获操作期间指定基于扫描的集成电路的输入约束; 指定时钟分组以将N个时钟域映射到G个时钟域组，其中N> G> 1; 根据输入约束和时钟分组将顺序电路模型转换为等效组合电路模型; 并根据输入约束在等效组合电路模型上产生刺激和测试响应。

公开(公告)号：US07512851B2

公开(公告)日：2009-03-31

申请号：US10901298

申请日：2004-07-29

申请人： Laung-Terng Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu ,  Fei-Sheng Hsu ,  Augusli Kifli ,  Shyh-Horng Lin ,  Shianling Wu ,  Shun-Miin (Sam) Wang ,  Ming-Tung Chang

发明人： Laung-Terng Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu ,  Fei-Sheng Hsu ,  Augusli Kifli ,  Shyh-Horng Lin ,  Shianling Wu ,  Shun-Miin (Sam) Wang ,  Ming-Tung Chang

IPC分类号： G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/318335 ,  G01R31/318547 ,  G01R31/318572 ,  G01R31/31905

摘要： A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.

摘要翻译： 一种方法和装置将以所选择的数据速率R1提供的压缩输入激励时分解复用和解压缩为以所选择的数据速率R2驱动的解压缩的激励，以驱动基于扫描的集成电路中的选定的扫描链，使用多个 的时分解复用器和时分复用器，用于将刺激和测试响应移入和移出高速I / O焊盘，以减少测试时间，测试成本和扫描引脚数。 还提出了一种用于合成时分复用器，解压缩器，压缩器和时分复用器的合成方法。

公开(公告)号：US07210082B1

公开(公告)日：2007-04-24

申请号：US11140579

申请日：2005-05-31

申请人： Khader S. Abdel-Hafez ,  Laung-Terng (L.-T.) Wang ,  Boryau (Jack) Sheu ,  Zhigang Wang ,  Zhigang Jiang

发明人： Khader S. Abdel-Hafez ,  Laung-Terng (L.-T.) Wang ,  Boryau (Jack) Sheu ,  Zhigang Wang ,  Zhigang Jiang

IPC分类号： G01R31/28 ,  G11B5/00 ,  G06F11/00

CPC分类号： G06F11/261 ,  G01R31/318307 ,  G01R31/318547

摘要： A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode. The method comprises compiling 704 the RTL (register-transfer level) or Gate-Level HDL (hardware description language) code 701 based on the Input Constraints 702 and a Foundry Library 703, into a Sequential Circuit Model 705. The Sequential Circuit Model 705 is then transformed 706 into an equivalent Combinational Circuit Model 707 for performing Forward and/or Backward Clock Analysis 708 to determine the driving and observing clocks for all inputs and outputs of all combinational logic gates in the Combinational Circuit Model 707. The analysis results are used for Uncontrollable/Unobservable Labeling 709 of selected inputs and outputs of the combinational logic gates. Finally, ATPG and/or Fault Simulation 710 are performed according to the Uncontrollable/Unobservable Labeling 709 to generate the HDL Test Benches and ATE Test Programs 711.

摘要翻译： 一种在所选择的扫描测试模式或选定的自测模式中，基于所选择的捕获操作中所选择的时钟顺序，在基于扫描的集成电路中执行ATPG（自动测试模式生成）和故障模拟的方法。 该方法包括将基于输入约束702和晶圆库703的RTL（寄存器传送级）或门级HDL（硬件描述语言）代码701编译成顺序电路模型705。 然后将顺序电路模型705转换为等效的组合电路模型707，以执行前向和/或后向时钟分析708，以确定组合电路模型707中所有组合逻辑门的所有输入和输出的驱动和观察时钟。 分析结果用于组合逻辑门的所选输入和输出的不可控/不可观察标签709。 最后，ATPG和/或故障模拟710根据不可控/不可观察的标签709执行，以产生HDL测试台和ATE测试程序711。

公开(公告)号：US07590905B2

公开(公告)日：2009-09-15

申请号：US11122244

申请日：2005-05-05

申请人： Khader S. Abdel-Hafez ,  Laung-Terng (L.-T.) Wang ,  Boryau (Jack) Sheu ,  Shianling Wu

发明人： Khader S. Abdel-Hafez ,  Laung-Terng (L.-T.) Wang ,  Boryau (Jack) Sheu ,  Shianling Wu

IPC分类号： G01R31/3177 ,  G01R31/40

CPC分类号： G01R31/318547

摘要： A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. A decompressor is embedded between N scan chains and M scan chains, where N

摘要翻译： 一种用于在基于扫描的集成电路中减少测试数据量和测试应用时间的流水线扫描压缩方法和装置，而不降低扫描测试模式或自检模式下扫描链操作的速度。 集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。 解压缩器被嵌入在N个扫描链和M个扫描链之间，其中N

公开(公告)号：US07231570B2

公开(公告)日：2007-06-12

申请号：US11122237

申请日：2005-05-05

申请人： Laung-Terng (L.-T.) Wang ,  Khader S. Abdel-Hafez ,  Boryau (Jack) Sheu ,  Shianling Wu

发明人： Laung-Terng (L.-T.) Wang ,  Khader S. Abdel-Hafez ,  Boryau (Jack) Sheu ,  Shianling Wu

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain including one or more scan cells coupled in series. Two or more decompressors are embedded between N compressed scan inputs and M scan chains, where N

摘要翻译： 一种多级扫描压缩方法和装置，用于在扫描测试模式或自检模式下降低扫描链操作的速度，减少测试数据量并在基于扫描的集成电路中测试应用时间。 基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。 将两个或更多个解压缩器嵌入在N个压缩扫描输入和M个扫描链之间，其中N

公开(公告)号：US20080276141A1

公开(公告)日：2008-11-06

申请号：US12216639

申请日：2008-07-09

申请人： Laung-Terng(L.-T.) Wang ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Khader S. Abdel-Hafez

发明人： Laung-Terng(L.-T.) Wang ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Khader S. Abdel-Hafez

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/318533 ,  G01R31/31926

摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor.

摘要翻译： 用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。 基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。 广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。 虚拟扫描控制器控制广播机构的操作。 系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。 进一步提出方法来重新排列所选扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且合成广播器和压缩器。

公开(公告)号：US07444567B2

公开(公告)日：2008-10-28

申请号：US10406592

申请日：2003-04-04

申请人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

发明人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

公开(公告)号：US07412672B1

公开(公告)日：2008-08-12

申请号：US11104651

申请日：2005-04-13

申请人： Laung-Terng Wang ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Khader S. Abdel-Hafez

发明人： Laung-Terng Wang ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Khader S. Abdel-Hafez

IPC分类号： G06F17/50

CPC分类号： G01R31/3177 ,  G01R31/318533 ,  G01R31/31926

摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor.

公开(公告)号：US07058869B2

公开(公告)日：2006-06-06

申请号：US10762571

申请日：2004-01-23

申请人： Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Hao-Jan Chao ,  Hsin-Po Wang

发明人： Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Hao-Jan Chao ,  Hsin-Po Wang

IPC分类号： G01R31/3177 ,  G01R31/3181 ,  G01R31/3185

CPC分类号： G01R31/318572 ,  G01R31/31705 ,  G01R31/318591

摘要： A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations. Computer-aided design (CAD) methods are then proposed to automatically synthesize the output-mask controller 301, output-mask network 304, input chain-mask controller and input-mask network, and to further generate test patterns according to the synthesized scan-based integrated circuit.

摘要翻译： 一种用于基于扫描的集成电路的调试，诊断和/或产量改进的方法和装置，其中嵌入在扫描核心303中的扫描链没有外部访问，例如当它们被图案发生器302和模式压缩器包围时的情况 305，使用DFT（设计为测试）技术，如Logic BIST（内置自检）或压缩扫描。 本发明包括一个输出屏蔽控制器301和一个输出屏蔽网络304，以允许设计者掩蔽所选择的扫描单元311在选定的模式压实器305中被压缩。 本发明还包括输入链掩模控制器和输入掩模网络，用于将恒定逻辑值驱动到所选扫描链的扫描链输入中，以允许设计者从扫描链保持时间违规恢复。 然后提出了计算机辅助设计（CAD）方法来自动合成输出掩模控制器301，输出掩模网络304，输入链掩模控制器和输入掩模网络，并根据合成的扫描 - 基于集成电路。