公开(公告)号：US08091002B2

公开(公告)日：2012-01-03

申请号：US12797302

申请日：2010-06-09

申请人： Laung-Terng Wang ,  Shianling Wu ,  Zhigang Jiang ,  Jinsong Liu ,  Hao-Jan Chao ,  Lizhen Yu ,  Feifei Zhao ,  Fangfang Li ,  Jianping Yan

发明人： Laung-Terng Wang ,  Shianling Wu ,  Zhigang Jiang ,  Jinsong Liu ,  Hao-Jan Chao ,  Lizhen Yu ,  Feifei Zhao ,  Fangfang Li ,  Jianping Yan

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594

摘要： A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

摘要翻译： 一种用于提供有序捕获时钟的方法，用于检测或定位N个时钟域内的故障，以及在扫描测试或自检模式下跨过集成电路或电路组件中的任何两个时钟域的故障，其中N> 1，每个时钟域具有一个 捕获时钟和多个扫描单元，每个捕获时钟包括多个捕获时钟脉冲; 所述方法包括：（a）在移入操作期间，在所述集成电路或电路组件中的所述N个时钟域内产生和移入N个测试刺激; （b）将所述捕获时钟的有序序列应用于所述N个时钟域内的所有所述扫描单元，所述捕获时钟的有序序列包括至少多个捕获时钟脉冲，所述捕获时钟脉冲以两个或更多个选定的捕获时钟以顺序排列，使得 在捕获操作期间，所有时钟域不会同时触发; 和（c）分析所有所述扫描单元的输出响应以定位其中的任何故障。

公开(公告)号：US20100287430A1

公开(公告)日：2010-11-11

申请号：US12797302

申请日：2010-06-09

申请人： Laung-Terng WANG ,  Shianling Wu ,  Zhigang Jiang ,  Jinsong Liu ,  Hao-Jan Chao ,  Lizhen Yu ,  Feifei Zhao ,  Fangfang Li ,  Jianping Yan

发明人： Laung-Terng WANG ,  Shianling Wu ,  Zhigang Jiang ,  Jinsong Liu ,  Hao-Jan Chao ,  Lizhen Yu ,  Feifei Zhao ,  Fangfang Li ,  Jianping Yan

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594

摘要： A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

摘要翻译： 一种用于提供有序捕获时钟的方法，用于检测或定位N个时钟域内的故障，以及在扫描测试或自检模式下跨过集成电路或电路组件中的任何两个时钟域的故障，其中N> 1，每个时钟域具有一个 捕获时钟和多个扫描单元，每个捕获时钟包括多个捕获时钟脉冲; 所述方法包括：（a）在移入操作期间，在所述集成电路或电路组件中的所述N个时钟域内产生和移入N个测试刺激; （b）将所述捕获时钟的有序序列应用于所述N个时钟域内的所有所述扫描单元，所述捕获时钟的有序序列包括至少多个捕获时钟脉冲，所述捕获时钟脉冲以两个或更多个选定的捕获时钟以顺序排列，使得 在捕获操作期间，所有时钟域不会同时触发; 和（c）分析所有所述扫描单元的输出响应以定位其中的任何故障。

公开(公告)号：US20100138709A1

公开(公告)日：2010-06-03

申请号：US12554437

申请日：2009-09-04

申请人： Laung-Terng WANG ,  Michael S. Hsiao ,  Hao-Jan Chao ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

发明人： Laung-Terng WANG ,  Michael S. Hsiao ,  Hao-Jan Chao ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

IPC分类号： G01R31/3177 ,  G06F11/27

CPC分类号： G01R31/318552

摘要： A hybrid clocking scheme for simultaneously detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path using at least n+1 at-speed clock pulses during a capture operation in a clock domain in a scan design or a scan-based BIST design, where 1

摘要翻译： 一种用于同时检测b周期（假）路径中的b周期路径延迟故障和c周期（假）路径中的c周期路径延迟故障的混合时钟方案，其使用至少n + 1 at- 在扫描设计或基于扫描的BIST设计中的时钟域中的捕获操作期间，速度时钟脉冲，其中1 <= b <= c <= n。 扫描设计或BIST设计包括多个扫描链，每个扫描链包括串联耦合的多个扫描单元。 该设计包括一个或多个时钟域，每个时钟域以其预期的工作频率或速度运行。 混合时钟方案包括至少一个速率移位时钟脉冲或一个在速捕获时钟脉冲，紧接着在捕获操作期间至少两个速度捕捉时钟脉冲，以同时检测b周期路径延迟故障，以及 时钟域内的c循环路径延迟故障。

公开(公告)号：US07783940B2

公开(公告)日：2010-08-24

申请号：US12155596

申请日：2008-06-06

申请人： Lizhen Yu ,  Shianling Wu ,  Zhigang Jiang ,  Laung-Terng Wang

发明人： Lizhen Yu ,  Shianling Wu ,  Zhigang Jiang ,  Laung-Terng Wang

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C29/4401 ,  G11C29/808

摘要： A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN−1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk−1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.

摘要翻译： 与k个冗余块相关联的N个基本块的存储器冗余重新配置。 如果基块有故障，数据将被写入基块和无缺陷冗余块; k复用器MUXRi，每个具有能够连接到冗余块的k个输入信号的N个输入信号（d0至dN-1）; N个多路复用器MUXi，其具有能够连接到N个输出信号（qi）的来自k个冗余块（R0至RK-1）和一个基本块（Ni）的k + 1个输入信号; 以及与每个多路复用器相关联的逻辑装置，以将多路复用器的输入信号转换成其输出信号。

公开(公告)号：US20090303815A1

公开(公告)日：2009-12-10

申请号：US12155596

申请日：2008-06-06

申请人： Lizhen Yu ,  Shianling Wu ,  Zhigang Jiang ,  Laung-Terng Wang

发明人： Lizhen Yu ,  Shianling Wu ,  Zhigang Jiang ,  Laung-Terng Wang

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C29/4401 ,  G11C29/808

摘要： A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN−1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk−1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.

摘要翻译： 与k个冗余块相关联的N个基本块的存储器冗余重新配置。 如果基块有故障，数据将被写入基块和无缺陷冗余块; k复用器MUXRi，每个具有能够连接到冗余块的k个输入信号的N个输入信号（d0至dN-1）; N个多路复用器MUXi，其具有能够连接到N个输出信号（qi）的来自k个冗余块（R0至RK-1）和一个基本块（Ni）的k + 1个输入信号; 以及与每个多路复用器相关联的逻辑装置，以将多路复用器的输入信号转换成其输出信号。

公开(公告)号：US08230282B2

公开(公告)日：2012-07-24

申请号：US13172046

申请日：2011-06-29

申请人： Nur A. Touba ,  Laung-Terng Wang ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

发明人： Nur A. Touba ,  Laung-Terng Wang ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

摘要翻译： 一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。 基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。 该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。 可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。 由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

公开(公告)号：US20120266036A1

公开(公告)日：2012-10-18

申请号：US13529686

申请日：2012-06-21

申请人： Nur A. TOUBA ,  Laung-Terng Wang ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

发明人： Nur A. TOUBA ,  Laung-Terng Wang ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318547

摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

摘要翻译： 一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。 基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。 该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。 可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。 由所述_combinational逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个所选故障的压缩扫描模式。

公开(公告)号：US20110047426A1

公开(公告)日：2011-02-24

申请号：US12546060

申请日：2009-08-24

申请人： Nur A. TOUBA ,  Laung-Terng Wang ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

发明人： Nur A. TOUBA ,  Laung-Terng Wang ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318547

摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

摘要翻译： 一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。 基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。 该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。 可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。 由所述_combinational逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个所选故障的压缩扫描模式。

公开(公告)号：US07996741B2

公开(公告)日：2011-08-09

申请号：US12546060

申请日：2009-08-24

申请人： Nur A. Touba ,  Laung-Terng Wang ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

发明人： Nur A. Touba ,  Laung-Terng Wang ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F9/455

CPC分类号： G01R31/318547

摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

摘要翻译： 一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。 基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。 该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。 可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。 由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

公开(公告)号：US20120110402A1

公开(公告)日：2012-05-03

申请号：US13222130

申请日：2011-08-31

申请人： Laung-Terng Wang ,  Nur Touba ,  Michael S. Hsiao ,  Shianling Wu ,  Zhigang Jiang

发明人： Laung-Terng Wang ,  Nur Touba ,  Michael S. Hsiao ,  Shianling Wu ,  Zhigang Jiang

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318558 ,  G01R31/318572

摘要： A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.

摘要翻译： 一种使用时分解复用/复用来测试基于扫描的3D集成电路（3DIC）的方法和装置，其允许在输入/输出焊盘处施加的高数据速率扫描图案转换为应用于每个的低数据速率扫描模式 嵌入模块在3DIC。 提出了一套3D设计指南，以减少测试次数和预键测试和后绑定测试所需的硅通孔数（TSV）。 该技术允许重新开发用于每个管芯（层）的前绑定测试的扫描模式，用于整个3DIC的后绑定测试。 它进一步减少测试应用时间，而不用担心I / O焊盘计数限制和故障覆盖损失的风险。