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公开(公告)号:US09780788B2
公开(公告)日:2017-10-03
申请号:US15332593
申请日:2016-10-24
IPC分类号: H03K19/003 , H03K19/096 , H03K3/037
CPC分类号: H03K19/00392 , H03K3/0375 , H03K19/0963
摘要: Embodiments of an sequential state element (SSE) capable of providing triple modular redundant (TMR) correction is disclosed. The SSE has a setup stage and a feedback stage. The setup stage is configured to generate an output bit signal having an output bit state while a clock signal is in the first clock state. The setup stage also generates a feedback input bit signal as feedback of the output bit state. However, the feedback stage is capable of providing TMR correction without this feedback signal. Instead, the feedback stage utilizes the second feedback input bit signal and a third feedback input bit signal from two other SSEs. Since TMR correction can be provided with just the second feedback input bit signal and the third feedback input bit signal, the power and area consumed by the SSE is reduced.
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公开(公告)号:US20170117895A1
公开(公告)日:2017-04-27
申请号:US15332593
申请日:2016-10-24
IPC分类号: H03K19/003 , H03K19/096 , H03K3/037
CPC分类号: H03K19/00392 , H03K3/0375 , H03K19/0963
摘要: Embodiments of an sequential state element (SSE) capable of providing triple modular redundant (TMR) correction is disclosed. The SSE has a setup stage and a feedback stage. The setup stage is configured to generate an output bit signal having an output bit state while a clock signal is in the first clock state. The setup stage also generates a feedback input bit signal as feedback of the output bit state. However, the feedback stage is capable of providing TMR correction without this feedback signal. Instead, the feedback stage utilizes the second feedback input bit signal and a third feedback input bit signal from two other SSEs. Since TMR correction can be provided with just the second feedback input bit signal and the third feedback input bit signal, the power and area consumed by the SSE is reduced.
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