公开(公告)号：US12210877B2

公开(公告)日：2025-01-28

申请号：US18118367

申请日：2023-03-07

Applicant: Lemon Inc. ,  Beijing Youzhuju Network Technology Co., Ltd.

Inventor： Viacheslav Dubeyko ,  Jian Wang

IPC: G06F9/30

Abstract: The present disclosure describes techniques for offloading computation based on an extended instruction set architecture (ISA). The extended ISA may be created based on identifying functions executed multiple times by a central processing unit (CPU). The extended ISA may comprise hashes corresponding to the functions and identifiers of extended operations associated with the functions. The extended operations may be converted from original operations of the functions. The extended operations may be executable by a storage device. The storage device may be associated with at least one computational core. Code may be synthesized based at least in part on the extended ISA. Computation of the synthesized code may be offloaded into the storage device.

公开(公告)号：US12164920B2

公开(公告)日：2024-12-10

申请号：US17984191

申请日：2022-11-09

Applicant: Lemon Inc. ,  Beijing Youzhuju Network Technology Co. Ltd.

Inventor： Viacheslav Dubeyko ,  Jian Wang

IPC: G06F12/12 ,  G06F9/30 ,  G06N3/04

Abstract: The present disclosure describes techniques for offloading data processing and knowledge synthesis. A set of flags may indicate information about the memory pages in a first memory and may be manageable by at least one central processing unit (CPU). A memory page may be flushed to a second memory if the memory page is associated with a first flag. The first flag may indicate that the memory page is ready to be flushed to the second memory. The second memory may be configured to store a sequence of states of each of the memory pages. Data patterns and relations among the data patterns may be determined by data processing units (DPUs) based on the sequence of states of each of the memory pages. A knowledge base may be built in a third memory based on the data patterns and the relations among the data patterns.

公开(公告)号：US12164482B2

公开(公告)日：2024-12-10

申请号：US17738579

申请日：2022-05-06

Applicant: Lemon Inc.

Inventor： Viacheslav Dubeyko ,  Jian Wang

IPC: G06F16/18 ,  G06F12/02

Abstract: The present disclosure describes techniques for improving data processing. At least one transaction may be generated by a file system driver associated with a host. Each transaction comprises logical block addresses (LBAs) and information associated with at least one function. The at least one transaction may be journaled into a computational storage for offloading data processing from the host to the computational storage. The computational storage comprises a persistent memory and at least one field-programmable gate array (FPGA) core. The offloading of the data processing comprises offloading journal replay operations to the computational storage. The journal replay operations comprise applying the at least one function to at least one subset of the LBAs by the at least one FPGA core.

公开(公告)号：US20230325240A1

公开(公告)日：2023-10-12

申请号：US17715530

申请日：2022-04-07

Applicant: Lemon Inc.

Inventor： Viacheslav Dubeyko ,  Jian Wang

IPC: G06F9/50 ,  G06F9/30 ,  G06F12/0882

CPC classification number: G06F9/5016 ,  G06F9/5022 ,  G06F9/30047 ,  G06F12/0882 ,  G06F2209/5011

Abstract: The present disclosure describes techniques for improved data processing. At least one management page may be generated by a host. The at least one management page comprises a plurality of management structures, and the at least one management page defines data instances, algorithms, and a computational environment. Computation may be initiated in a memory pool by performing a write operation of the at least one management page into the memory pool. The memory pool comprises a persistent memory and a plurality of field-programmable gate array (FPGA) cores. The computation in the memory pool comprises parallel data processing by at least a subset of the plurality of FPGA cores.

公开(公告)号：US20230176921A1

公开(公告)日：2023-06-08

申请号：US18104947

申请日：2023-02-02

Applicant: Lemon Inc. ,  Beijing Youzhuju Network Technology Co., Ltd.

Inventor： Viacheslav Dubeyko ,  Jian Wang

IPC: G06F9/50

CPC classification number: G06F9/5061 ,  G06F2209/509 ,  G06F2209/5018

Abstract: The present disclosure describes techniques for offloading computation into a storage space. A plurality of streams may be created in a storage device in response to receiving information of defining the plurality of streams from an application. Each of the plurality of streams may be configured to contain a sequence of objects of a same type among a plurality of types of objects. The plurality of types of objects may be associated with one or more applications. Each of the plurality of streams may comprise a thread descriptor indicative of at least one algorithm to be applied to the sequence of objects. Data may be added to the plurality of streams. Computation associated with the plurality of streams may be offloaded into the storage device. The storage device may be associated with at least one computational core.

公开(公告)号：US20240152358A1

公开(公告)日：2024-05-09

申请号：US17984191

申请日：2022-11-09

Applicant: Lemon Inc. ,  Beijing Youzhuju Network Technology Co. Ltd.

Inventor： Viacheslav Dubeyko ,  Jian Wang

IPC: G06F9/30 ,  G06N3/04

CPC classification number: G06F9/30047 ,  G06F9/30032 ,  G06F9/30189 ,  G06N3/04

Abstract: The present disclosure describes techniques for offloading data processing and knowledge synthesis. A set of flags may indicate information about the memory pages in a first memory and may be manageable by at least one central processing unit (CPU). A memory page may be flushed to a second memory if the memory page is associated with a first flag. The first flag may indicate that the memory page is ready to be flushed to the second memory. The second memory may be configured to store a sequence of states of each of the memory pages. Data patterns and relations among the data patterns may be determined by data processing units (DPUs) based on the sequence of states of each of the memory pages. A knowledge base may be built in a third memory based on the data patterns and the relations among the data patterns.

公开(公告)号：US20230401096A1

公开(公告)日：2023-12-14

申请号：US17806856

申请日：2022-06-14

Applicant: Lemon Inc.

Inventor： Viacheslav Dubeyko ,  Jian Wang

IPC: G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5022 ,  G06F9/5044 ,  G06F9/5083 ,  G06F2209/5011

Abstract: A storage system includes a host device and a heterogeneous memory pool. The host device includes an application and a memory allocator stored thereon. The heterogeneous memory pool includes a volatile or non-volatile memory component, a persistent memory component, and a computational component. The computational component is in communication with the persistent memory component and the volatile or non-volatile memory component. The host device is in communication with the heterogeneous memory pool, via the memory allocator, to offload computations from the host device to the heterogenous memory pool.

公开(公告)号：US20230244635A1

公开(公告)日：2023-08-03

申请号：US18133263

申请日：2023-04-11

Applicant: Lemon Inc. ,  Beijing Youzhuju Network Technology Co., Ltd.

Inventor： Viacheslav Dubeyko ,  Jian Wang

IPC: G06F16/11 ,  G06F16/174 ,  G06F16/178 ,  G06F16/17 ,  G06F16/172

CPC classification number: G06F16/122 ,  G06F16/1744 ,  G06F16/178 ,  G06F16/1734 ,  G06F16/172

Abstract: The present disclosure describes techniques for improving performance of file system operations. Dirty memory pages may be copied from a file system into a memory associated with first hardware accelerator associated with a host. Content of the memory pages may be compressed by one or more cores of the hardware accelerator. The compressed data may be compacted into a payload area of at least one log. Metadata of the at least one log may be prepared by the one or more cores of the hardware accelerator. The at least one log may be flushed into a storage device. A read operation may be performed on the at least one log. On a read path, in response to determining that a size of data from a plurality of logs is greater than a predetermined threshold, a new log may be created by combining the data using compression by a second hardware accelerator associated with the storage device.

公开(公告)号：US12118397B2

公开(公告)日：2024-10-15

申请号：US17945843

申请日：2022-09-15

Applicant: Lemon Inc. ,  Beijing Youzhuju Network Technology Co. Ltd.

Inventor： Viacheslav Dubeyko ,  Jian Wang

IPC: G06F9/50 ,  G06F9/48 ,  G06F15/78

CPC classification number: G06F9/5027 ,  G06F9/4843 ,  G06F15/7821

Abstract: The present disclosure describes techniques for accelerating data processing by offloading thread computation. An application may be started based on creating and executing a process by a host, the process associated with a plurality of threads. Creating a plurality of computation threads on a storage device may be requested based on determining that the storage device represents a computational storage. The plurality of computation threads may be created based on preloading a plurality of libraries in the storage device. The plurality of libraries may comprise executable codes associated with the plurality of threads. Data processing associated with the plurality of threads may be offloaded to the storage device using the plurality of computation threads. Activities associated with the plurality of computation threads may be managed by the process.

公开(公告)号：US20230376242A1

公开(公告)日：2023-11-23

申请号：US17746831

申请日：2022-05-17

Applicant: Lemon Inc.

Inventor： Viacheslav Dubeyko ,  Jian Wang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0679 ,  G06F3/0604

Abstract: A system includes a first hardware architecture and computational storage. The computational storage includes a second hardware architecture, and memory storing instructions that, when executed by the second hardware architecture, causes the system to perform a first set of operations. The first set of operations include receiving instructions from the first hardware architecture, performing one or more computations on data stored in the second hardware architecture, based on the received instructions, and transmitting a result to the first hardware architecture, based on the one or more performed computations.