公开(公告)号：US20090049248A1

公开(公告)日：2009-02-19

申请号：US11839663

申请日：2007-08-16

申请人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

发明人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0851 ,  G06F12/0864

摘要： A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

摘要翻译： 一种方法和计算机系统，用于通过重新配置扇区到片分配和较低的高速缓存寻址方案来减少具有扇区和分片的低级高速缓存的高速缓存子系统中的布线拥塞，所需的房地产和访问延迟。 通过这种分配，具有不连续地址的扇区被放置在相同的片内，并且基于对高速缓存片内的可寻址扇区的这种重新分配，可以在两级低级高速缓存之间进行简化布线方案。 此外，低速缓存有效地址标签被重新配置，使得先前分配用于识别扇区和片的地址字段相对于地址标签内的彼此的位置被切换。 地址位的这种重新分配使得能够基于指示的扇区进行直接片寻址。

公开(公告)号：US08433851B2

公开(公告)日：2013-04-30

申请号：US11839663

申请日：2007-08-16

申请人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

发明人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0851 ,  G06F12/0864

摘要： A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

摘要翻译： 一种方法和计算机系统，用于通过重新配置扇区到片分配和较低的高速缓存寻址方案来减少具有扇区和分片的低级高速缓存的高速缓存子系统中的布线拥塞，所需的房地产和访问延迟。 通过这种分配，具有不连续地址的扇区被放置在相同的片内，并且基于对高速缓存片内的可寻址扇区的这种重新分配，可以在两级低级高速缓存之间进行简化布线方案。 此外，低速缓存有效地址标签被重新配置，使得先前分配用于识别扇区和片的地址字段相对于地址标签内的彼此的位置被切换。 地址位的这种重新分配使得能够基于指示的扇区进行直接片寻址。

公开(公告)号：US07480772B2

公开(公告)日：2009-01-20

申请号：US11835984

申请日：2007-08-08

申请人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

发明人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

公开(公告)号：US07454577B2

公开(公告)日：2008-11-18

申请号：US11055476

申请日：2005-02-10

申请人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

发明人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F13/00

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

公开(公告)号：US07827354B2

公开(公告)日：2010-11-02

申请号：US11923952

申请日：2007-10-25

申请人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Bradley David McCredie ,  William John Starke

发明人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Bradley David McCredie ,  William John Starke

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/127

摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。 在替代实施例中，利用直接干预来访问相同级别的受害者缓存。

公开(公告)号：US20090083489A1

公开(公告)日：2009-03-26

申请号：US12325266

申请日：2008-12-01

申请人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke

发明人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F12/08

CPC分类号： G06F12/0851 ,  G06F12/0811

摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

摘要翻译： 缓存存储器将具有单个访问/命令端口的高速缓存阵列逻辑地分区成至少两个切片，并且使用第一目录来访问第一阵列片，同时使用第二目录来访问第二阵列片，但是从高速缓存目录 使用控制单个访问/命令端口的单个缓存仲裁器进行管理。 在一个实施例中，每个高速缓存目录具有其自己的目录仲裁器来处理冲突的内部请求，并且目录仲裁器与高速缓存仲裁器通信。 高速缓存阵列布置有高速缓存扇区的行和列，其中高速缓存行分布在不同行和列中的扇区之间，其中一部分给定高速缓存行位于具有第一延迟的第一列中，并且给定的另一部分 高速缓存线位于具有大于第一等待时间的第二等待时间的第二列中。

公开(公告)号：US07305522B2

公开(公告)日：2007-12-04

申请号：US11056649

申请日：2005-02-12

申请人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Bradley David McCredie ,  William John Starke

发明人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Bradley David McCredie ,  William John Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/127

摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。 在替代实施例中，利用直接干预来访问相同级别的受害者缓存。

公开(公告)号：US07490200B2

公开(公告)日：2009-02-10

申请号：US11054924

申请日：2005-02-10

申请人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke

发明人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F12/08

CPC分类号： G06F12/0851 ,  G06F12/0811

摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry. The cache array may be arranged with rows and columns of cache sectors wherein a given cache line is spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency. The cache array outputs different sectors of the given cache line in successive clock cycles based on the latency of a given sector.

摘要翻译： 高速缓存存储器将具有单个访问/命令端口的高速缓存阵列逻辑地分割成至少两个切片，并且使用第一高速缓存目录访问第一高速缓存阵列切片，同时使用第二高速缓存目录来访问第二高速缓存阵列切片，但是访问 从缓存目录中使用单个缓存仲裁器来管理单个访问/命令端口。 在说明性实施例中，每个高速缓存目录具有其自己的目录仲裁器来处理冲突的内部请求，并且目录仲裁器与缓存仲裁器通信。 与处理器核心相关联的地址标签被从处理器核心以指定的位发送，指定的位将地址标签与只有一个高速缓存阵列片相关联，其相应的目录确定地址标签是否与当前有效的高速缓存条目匹配。 高速缓存阵列可以布置有高速缓存扇区的行和列，其中给定的高速缓存行分布在不同行和列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列和另一个 给定高速缓存行的一部分位于具有大于第一等待时间的第二等待时间的第二列中。 缓存阵列基于给定扇区的等待时间在连续的时钟周期中输出给定高速缓存行的不同扇区。

公开(公告)号：US08001330B2

公开(公告)日：2011-08-16

申请号：US12325266

申请日：2008-12-01

申请人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke

发明人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F13/00

CPC分类号： G06F12/0851 ,  G06F12/0811

摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

摘要翻译： 缓存存储器将具有单个访问/命令端口的高速缓存阵列逻辑地分区成至少两个切片，并且使用第一目录来访问第一阵列片，同时使用第二目录来访问第二阵列片，但是从高速缓存目录 使用控制单个访问/命令端口的单个缓存仲裁器进行管理。 在一个实施例中，每个高速缓存目录具有其自己的目录仲裁器来处理冲突的内部请求，并且目录仲裁器与高速缓存仲裁器通信。 高速缓存阵列布置有高速缓存扇区的行和列，其中高速缓存行分布在不同行和列中的扇区之间，其中一部分给定高速缓存行位于具有第一延迟的第一列中，并且给定的另一部分 高速缓存线位于具有大于第一等待时间的第二等待时间的第二列中。

公开(公告)号：US07783841B2

公开(公告)日：2010-08-24

申请号：US11836965

申请日：2007-08-10

申请人： James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Jeffrey Adam Stuecheli

发明人： James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Jeffrey Adam Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。 高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。