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公开(公告)号：US08798129B2
公开(公告)日：2014-08-05
申请号：US13343591
申请日：2012-01-04
IPC分类号： H03H7/30
CPC分类号： H03H17/04 , H03H2017/0477
摘要： A BIIR system includes a first delay line for receiving at least one input data sample and generating delayed input samples as a function of the input data sample. The BIIR system further includes a second delay line including multiple delay elements connected in series for generating delayed output samples. An input of one of the delay elements receives at least one output data sample of the BIIR system. A summation element in the BIIR system generates the output data sample of the BIIR system as a function of an addition of at least first and second signals and a subtraction of at least a third signal. The third signal includes a first delayed output sample generated by the second delay line multiplied by a first prescribed value. The first delayed output sample and the output data sample are temporally nonadjacent to one another.
摘要翻译： BIIR系统包括用于接收至少一个输入数据样本并根据输入数据样本产生延迟输入样本的第一延迟线。 BIIR系统还包括第二延迟线，包括串联连接的多个延迟元件，用于产生延迟的输出采样。 一个延迟元件的输入接收BIIR系统的至少一个输出数据样本。 BIIR系统中的求和元素根据添加至少第一和第二信号以及减去至少第三信号的函数产生BIIR系统的输出数据样本。 第三信号包括由第二延迟线产生的第一延迟输出采样乘以第一规定值。 第一个延迟输出样本和输出数据样本在时间上不相邻。
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2.发明授权Sequentially packing mask selected bits from plural words in circularly coupled register pair for transferring filled register bits to memory 有权顺序打包圆形耦合寄存器对中的多个字中选定的位，以将填充的寄存器位传送到存储器公开(公告)号：US08607033B2
公开(公告)日：2013-12-10
申请号：US12875400
申请日：2010-09-03
IPC分类号： G06F9/312
CPC分类号： G06F12/04 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate a plurality of packed items by extracting-and-packing a plurality of input data words based on a bit mask. The second circuit may be configured to (i) receive the packed items from the first circuit, (ii) sequentially buffer the packed items in a plurality of registers, at least one of the packed items crossing a boundary between a current one of the registers and a next one of the registers, and (iii) write the packed items in the current register to a memory in response to the current register becoming full.
摘要翻译： 公开了一种具有第一电路和第二电路的装置。 第一电路可以被配置为通过基于位掩码提取和打包多个输入数据字来生成多个打包项。 第二电路可以被配置为（i）从第一电路接收打包的项目，（ii）顺序地缓冲多个寄存器中的打包项目，至少一个打包项目穿过当前一个寄存器 和下一个寄存器，以及（iii）响应于当前寄存器变满而将当前寄存器中的打包项目写入存储器。
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公开(公告)号：US20130219131A1
公开(公告)日：2013-08-22
申请号：US13400212
申请日：2012-02-20
IPC分类号： G06F12/00
CPC分类号： G06F12/02 , G06F9/3013 , G06F9/3555 , G06F12/06
摘要： An apparatus having a memory and a controller is disclosed. The controller may be configured to (i) receive a read request from a processor, the read request comprising a first value and a second value, (ii) where the read request is an indirect memory access, (a) generate a first address in response to the first value, (b) read data stored in the memory at the first address and (c) generate a second address in response to the second value and the data, (iii) where the read request is a direct memory access, generate the second address in response to the second value and (iv) read a requested data stored in the memory at the second address.
摘要翻译： 公开了一种具有存储器和控制器的装置。 控制器可以被配置为（i）从处理器接收读取请求，所述读取请求包括第一值和第二值，（ii）其中所述读取请求是间接存储器访问，（a）生成第一地址 响应于第一值，（b）读取存储在第一地址的存储器中的数据，（c）响应于第二值和数据产生第二地址，（iii）读取请求是直接存储器存取， 响应于第二值产生第二地址，以及（iv）在第二地址处读取存储在存储器中的请求数据。
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4.发明授权Avoiding stall in processor pipeline upon read after write resource conflict when intervening write present 有权在写入资源冲突时，在读写时避免在处理器管道中停止写入公开(公告)号：US08499139B2
公开(公告)日：2013-07-30
申请号：US12855201
申请日：2010-08-12
IPC分类号： G06F9/38
CPC分类号： G06F9/3838 , G06F9/3857
摘要： An apparatus having a processor and a circuit is disclosed. The processor generally has a pipeline. The circuit may be configured to (i) detect a first write instruction in the pipeline that writes to a resource, (ii) stall a read instruction in the pipeline where (a) a first read-after-write conflict exists between the first write instruction and the read instruction and (b) no other write instruction to the resource is scheduled between the first write instruction and the read instruction and (iii) not stall the read instruction due to the first read-after-write conflict where a second write instruction to the resource is scheduled between the first write instruction and the read instruction.
摘要翻译： 公开了一种具有处理器和电路的装置。 处理器通常具有管道。 电路可以被配置为（i）检测在流水线中写入资源的第一写入指令，（ii）停止在流水线中的读取指令，其中（a）在第一写入之间存在第一写后冲突冲突 指令和读取指令，以及（b）在第一写入指令和读取指令之间调度对资源的其他写入指令，以及（iii）由于第一次写入后写入冲突而导致的读取指令停止， 在第一写指令和读指令之间调度对资源的指令。
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公开(公告)号：US20130117532A1
公开(公告)日：2013-05-09
申请号：US13290364
申请日：2011-11-07
IPC分类号： G06F12/08
CPC分类号： G06F12/0607
摘要： An apparatus having a plurality of memory blocks and a circuit is disclosed. The circuit may be configured to (i) generate a second address by removing one or more first bits of a first address from one or more first locations defined by a first value, (ii) generate a third address by adding an offset value to the second address and (iii) generate a fourth address by inserting a selected one of a plurality of modifiers into the third address. The selected modifier may be inserted into the third address at the first locations. Each modifier is generally associated with a respective one of a plurality of buffers formed in the memory blocks. The circuit may also be configured to access the respective buffer of the fourth address.
摘要翻译： 公开了具有多个存储块和电路的装置。 电路可以被配置为：（i）通过从由第一值定义的一个或多个第一位置去除第一地址的一个或多个第一位来产生第二地址，（ii）通过将偏移值加到第 第二地址，以及（iii）通过将多个修饰符中的所选择的一个插入第三地址来生成第四地址。 所选择的修饰符可以在第一位置被插入到第三地址中。 每个修改器通常与形成在存储器块中的多个缓冲器中的相应一个缓冲器相关联。 电路还可以被配置为访问第四地址的相应缓冲器。
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公开(公告)号：US20130107957A1
公开(公告)日：2013-05-02
申请号：US13285353
申请日：2011-10-31
IPC分类号： H04N7/32
CPC分类号： H04N19/11 , H04N19/147 , H04N19/176 , H04N19/423 , H04N19/593
摘要： An apparatus having a memory and a circuit is disclosed. The memory may be configured to store a picture being encoded. The circuit may be configured to calculate a plurality of first arrays directly from a plurality of neighboring samples around a current block of the picture. Each first array generally represents a respective one of a plurality of intra-prediction modes. Each first array may be spatially smaller than the current block. The circuit may also be configured to calculate a second array from a plurality of current samples in the current block. The second array may spatially match the first arrays. The circuit may be further configured to generate a plurality of scores of the intra-prediction modes by comparing the first arrays with the second array and select a given one of the intra-prediction modes corresponding to a lowest of the scores to encode the current block.
摘要翻译： 公开了一种具有存储器和电路的装置。 存储器可以被配置为存储被编码的图像。 电路可以被配置为直接从图像的当前块周围的多个相邻样本计算多个第一阵列。 每个第一阵列通常表示多个帧内预测模式中的相应一个。 每个第一阵列可以在空间上小于当前块。 电路还可以被配置为从当前块中的多个当前样本计算第二阵列。 第二阵列可以在空间上匹配第一阵列。 该电路还可以被配置为通过将第一阵列与第二阵列进行比较来产生多个分数的帧内预测模式，并且选择与最低分数相对应的帧内预测模式中的给定一个来编码当前块 。
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7.发明申请公开(公告)号：US20120042152A1
公开(公告)日：2012-02-16
申请号：US12855201
申请日：2010-08-12
CPC分类号： G06F9/3838 , G06F9/3857
摘要： An apparatus having a processor and a circuit is disclosed. The processor generally has a pipeline. The circuit may be configured to (i) detect a first write instruction in the pipeline that writes to a resource, (ii) stall a read instruction in the pipeline where (a) a first read-after-write conflict exists between the first write instruction and the read instruction and (b) no other write instruction to the resource is scheduled between the first write instruction and the read instruction and (iii) not stall the read instruction due to the first read-after-write conflict where a second write instruction to the resource is scheduled between the first write instruction and the read instruction.
摘要翻译： 公开了一种具有处理器和电路的装置。 处理器通常具有管道。 电路可以被配置为（i）检测在流水线中写入资源的第一写入指令，（ii）停止在流水线中的读取指令，其中（a）在第一写入之间存在第一写后冲突冲突 指令和读取指令，以及（b）在第一写入指令和读取指令之间调度对资源的其他写入指令，以及（iii）由于第一次写入后写入冲突而导致的读取指令停止， 在第一写指令和读指令之间调度对资源的指令。
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8.发明申请公开(公告)号：US20130159367A1
公开(公告)日：2013-06-20
申请号：US13330436
申请日：2011-12-19
CPC分类号： G06F7/5336
摘要： A multiplier circuit for generating a product of at least first and second multiplicands includes encoding circuitry comprising a plurality of encoders. Each of the encoders is operative to receive at least a subset of bits of the first multiplicand and to generate a partial product corresponding to the subset of bits of the first multiplicand. The encoding circuitry is further operative to incorporate a negation of the product as a function of at least a first control signal supplied to the multiplier circuit. The multiplier circuit further includes summation circuitry coupled with the encoding circuitry. The summation circuitry is operative to sum each of the partial products generated by the encoding circuitry to thereby generate the product without performing post-incrementation.
摘要翻译： 用于产生至少第一和第二被乘数的乘积的乘法器电路包括包括多个编码器的编码电路。 每个编码器操作以接收第一被乘数的比特的至少一个子集，并且生成对应于第一被乘数的比特的子集的部分乘积。 编码电路还可操作以将产品的否定作为至少提供给乘法器电路的第一控制信号的函数。 乘法器电路还包括与编码电路耦合的求和电路。 求和电路用于对由编码电路产生的每个部分乘积进行求和，从而生成产品而不执行后递增。
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公开(公告)号：US20130136181A1
公开(公告)日：2013-05-30
申请号：US13307393
申请日：2011-11-30
IPC分类号： H04N7/32
CPC分类号： H04N19/533 , H04N19/433
摘要： An apparatus having a cache and a processor. The cache may be configured to (i) buffer a first subset of reference samples of a reference picture to facilitate a motion estimation of a current block and (ii) prefetch a second subset of the reference samples while a first search pattern is being tested. The first search pattern used in the motion estimation generally defines multiple motion vectors to test. The reference samples of the second subset may be utilized by a second search pattern in the motion estimation of the current block. The prefetch of the second subset may be based on a geometry of the first search pattern and scores of the motion vectors already tested. The processor may be configured to calculate the scores of the motion vectors by a block comparison of the reference samples to the current block according to the first search pattern.
摘要翻译： 具有高速缓存和处理器的装置。 高速缓存可以被配置为（i）缓冲参考图片的参考样本的第一子集，以促进当前块的运动估计，以及（ii）在测试第一搜索模式的同时预取参考样本的第二子集。 在运动估计中使用的第一搜索模式通常定义要测试的多个运动矢量。 第二子集的参考样本可以由当前块的运动估计中的第二搜索模式来利用。 第二子集的预取可以基于第一搜索模式的几何形状和已经测试的运动矢量的分数。 处理器可以被配置为根据第一搜索模式通过参考样本与当前块的块比较来计算运动矢量的得分。
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10.发明申请Direct Memory Access With On-The-Fly Generation of Frame Information For Unrestricted Motion Vectors 审中-公开直接存储器访问，用于不受限制的运动矢量的帧信息的即时生成公开(公告)号：US20130094586A1
公开(公告)日：2013-04-18
申请号：US13274422
申请日：2011-10-17
IPC分类号： H04N7/32
CPC分类号： H04N19/427
摘要： A method for performing motion estimation based on at least a first VOP stored in a memory includes the steps of: receiving a request to read a data block indicative of at least a portion of the first VOP for predicting a second VOP that is temporally adjacent to the first VOP; utilizing a DMA module for determining whether the data block is a UMV block; translating a block address for retrieving at least a portion of the data block from the memory as a function of one or more parameters generated by the DMA module; and generating a complete data block as a function of the portion of the data block retrieved from the memory and the one or more parameters generated by the DMA module.
摘要翻译： 一种用于基于存储在存储器中的至少第一VOP执行运动估计的方法包括以下步骤：接收读取指示第一VOP的至少一部分的数据块的请求，用于预测与时间上相邻的第二VOP 第一个VOP; 利用DMA模块来确定数据块是否是UMV块; 根据由所述DMA模块生成的一个或多个参数来转换用于从所述存储器检索所述数据块的至少一部分的块地址; 以及根据从存储器检索的数据块的部分和由DMA模块生成的一个或多个参数，生成完整的数据块。
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