公开(公告)号：US07668188B2

公开(公告)日：2010-02-23

申请号：US11353886

申请日：2006-02-14

申请人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

发明人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L1/0071 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/0075 ,  H04L1/08 ,  H04L1/1812 ,  H04L1/1845 ,  H04L2001/0093

摘要： Methods and systems for processing signals in a communication system are disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while simultaneously storing on-chip, a portion of the plurality of information bits in the received bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and the storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits may be partitioned into a functional data processing path and a functional address processing path.

摘要翻译： 公开了用于在通信系统中处理信号的方法和系统，并且可以包括在单个芯片内接收的HSDPA比特流的流水线处理。 流水线可以包括计算接收的HSDPA比特流中的多个信息比特的当前部分的存储器地址，同时在片上存储接收到的当前部分之后的接收比特流中的多个信息比特的一部分 。 可以在计算和存储期间对接收到的HSDPA比特流中当前部分之前的多个信息比特的一部分进行解码。 可以在不使用缓冲器的情况下实现多个信息比特的当前部分的存储器地址的计算。 多个信息位的处理可以被划分为功能数据处理路径和功能地址处理路径。

公开(公告)号：US08036239B2

公开(公告)日：2011-10-11

申请号：US12709871

申请日：2010-02-22

申请人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

发明人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L1/0071 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/0075 ,  H04L1/08 ,  H04L1/1812 ,  H04L1/1845 ,  H04L2001/0093

摘要： A method for processing signals in a communication system is disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while storing on-chip, a portion of the plurality of information bits in the received HSDPA bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits in the received HSDPA bitstream may be partitioned into a functional data processing path and functional address processing path.

摘要翻译： 公开了一种用于在通信系统中处理信号的方法，并且可以包括在单个芯片内接收的HSDPA比特流的流水线处理。 流水线可以包括计算接收的HSDPA比特流中的多个信息比特的当前部分的存储器地址，同时在片上存储在当前部分之后的所接收的HSDPA比特流中的多个信息比特的一部分 。 在计算和存储期间，在当前部分之前的接收的HSDPA比特流中的多个信息比特的一部分可以被解码。 可以在不使用缓冲器的情况下实现多个信息比特的当前部分的存储器地址的计算。 可以将所接收的HSDPA比特流中的多个信息比特的处理划分为功能数据处理路径和功能地址处理路径。

公开(公告)号：US20100150165A1

公开(公告)日：2010-06-17

申请号：US12709871

申请日：2010-02-22

申请人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

发明人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

IPC分类号： H04L12/56

CPC分类号： H04L1/0071 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/0075 ,  H04L1/08 ,  H04L1/1812 ,  H04L1/1845 ,  H04L2001/0093

摘要： A method for processing signals in a communication system is disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while storing on-chip, a portion of the plurality of information bits in the received HSDPA bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits in the received HSDPA bitstream may be partitioned into a functional data processing path and functional address processing path.

摘要翻译： 公开了一种用于在通信系统中处理信号的方法，并且可以包括在单个芯片内接收的HSDPA比特流的流水线处理。 流水线可以包括计算接收的HSDPA比特流中的多个信息比特的当前部分的存储器地址，同时在片上存储在当前部分之后的所接收的HSDPA比特流中的多个信息比特的一部分 。 在计算和存储期间，在当前部分之前的接收的HSDPA比特流中的多个信息比特的一部分可以被解码。 可以在不使用缓冲器的情况下实现多个信息比特的当前部分的存储器地址的计算。 可以将所接收的HSDPA比特流中的多个信息比特的处理划分为功能数据处理路径和功能地址处理路径。

公开(公告)号：US08068681B2

公开(公告)日：2011-11-29

申请号：US12839591

申请日：2010-07-20

申请人： Taiyi Cheng ,  Mark Hahm ,  Li Fung Chang

发明人： Taiyi Cheng ,  Mark Hahm ,  Li Fung Chang

IPC分类号： G06K9/36

CPC分类号： H04N19/42

摘要： A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.

摘要翻译： 描述了集成嵌入式图像和视频加速器中流水线处理的方法和系统。 在集成嵌入式图像和视频加速器中用于流水线处理的系统的方面可以包括能够对单个芯片内的视频数据进行流水线处理的电路，其中流水线处理还可以包括对视频数据块进行解码，同时对先前 解码的视频数据块。 系统的方面还可以包括能够在单个芯片内转换所述视频数据的块的电路，同时在所述单个芯片内同时编码先前转换的视频数据块。

公开(公告)号：US07760951B2

公开(公告)日：2010-07-20

申请号：US11353528

申请日：2006-02-14

申请人： Taiyi Cheng ,  Mark Hahm ,  Li Fung Chang

发明人： Taiyi Cheng ,  Mark Hahm ,  Li Fung Chang

IPC分类号： G06K9/36

CPC分类号： H04N19/42

摘要： A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.

摘要翻译： 描述了集成嵌入式图像和视频加速器中流水线处理的方法和系统。 在集成嵌入式图像和视频加速器中用于流水线处理的系统的方面可以包括能够对单个芯片内的视频数据进行流水线处理的电路，其中流水线处理还可以包括对视频数据块进行解码，同时对先前 解码的视频数据块。 系统的方面还可以包括能够在单个芯片内转换所述视频数据的块的电路，同时在所述单个芯片内同时编码先前转换的视频数据块。

公开(公告)号：US20080132190A1

公开(公告)日：2008-06-05

申请号：US11607438

申请日：2006-12-01

申请人： Hongwei Kong ,  Nelson Sollenberger ,  Li Fung Chang ,  Zoran Kostic ,  Mark Hahm

发明人： Hongwei Kong ,  Nelson Sollenberger ,  Li Fung Chang ,  Zoran Kostic ,  Mark Hahm

IPC分类号： H04B1/10

CPC分类号： H04B1/7115 ,  H04B1/7117 ,  H04B2201/70701

摘要： Certain aspects of a method and system for delay matching in a rake receiver are disclosed. Aspects of one method may include compensating for a delay associated with at least one or both of the following in a rake receiver: a control channel and a data channel, prior to individual processing of received data by the data channel and individual processing of received data by the control channel. The data channel or the dedicated physical channel (DPCH) may be delayed with respect to the control channel, which may comprise, for example, the common pilot control channel (CPICH), by a particular time period.

摘要翻译： 公开了用于耙式接收机中的延迟匹配的方法和系统的某些方面。 一种方法的方面可以包括在耙式接收机中补偿与以下中的至少一个或两者相关联的延迟：控制信道和数据信道，在数据信道对接收到的数据进行单独处理之前，以及接收数据的单独处理 由控制通道。 数据信道或专用物理信道（DPCH）可以相对于可以包括例如公共导频控制信道（CPICH）的控制信道延迟特定时间段。

公开(公告)号：US08503506B2

公开(公告)日：2013-08-06

申请号：US13588297

申请日：2012-08-17

申请人： Mark Hahm ,  Wei Luo ,  Arkady Molev-Shteiman ,  Hongwei Kong ,  Xiao-Feng Qi ,  Li Fung Chang ,  Nelson Sollenberger

发明人： Mark Hahm ,  Wei Luo ,  Arkady Molev-Shteiman ,  Hongwei Kong ,  Xiao-Feng Qi ,  Li Fung Chang ,  Nelson Sollenberger

IPC分类号： H04B1/707

CPC分类号： H04B1/712 ,  H04J11/0063 ,  H04J13/0044 ,  H04J13/0048

摘要： Aspects of a method and system for interference suppression in WCDMA systems may include one or more circuits that are operable to receive a plurality of multipath signals via one or more receiving antennas. A plurality of weighting factor values may be computed based on the received multipath signals. Estimated signals may be based on the weighting factor values. Residual signals may be generated based on received signals and the estimated signals. Addback signals may be generated based on the estimated signals and the residual signals. Updated estimated signals may be generated based on the addback signals and the weighting factor values. Incremental signals may be generated based on the updated estimated signals and addback signals. Updated residual signals may be generated based on the incremental signals and previous residual signals. The interference suppressed signals may be generated based on the updated residual signals and updated estimated signals.

摘要翻译： 用于WCDMA系统中的干扰抑制的方法和系统的方面可以包括可操作以经由一个或多个接收天线接收多个多径信号的一个或多个电路。 可以基于接收的多路径信号来计算多个加权因子值。 估计信号可以基于加权因子值。 可以基于接收的信号和估计的信号来产生残余信号。 可以基于估计的信号和残留信号来生成附加信号。 可以基于附加信号和加权因子值来生成更新的估计信号。 可以基于更新的估计信号和加法信号来产生增量信号。 可以基于增量信号和先前的剩余信号来生成更新的残留信号。 可以基于更新的残差信号和更新的估计信号来产生干扰抑制信号。

公开(公告)号：US08831139B2

公开(公告)日：2014-09-09

申请号：US11607438

申请日：2006-12-01

申请人： Hongwei Kong ,  Nelson Sollenberger ,  Li Fung Chang ,  Zoran Kostic ,  Mark Hahm

发明人： Hongwei Kong ,  Nelson Sollenberger ,  Li Fung Chang ,  Zoran Kostic ,  Mark Hahm

IPC分类号： H04B1/10 ,  H04B1/7115 ,  H04B1/7117

CPC分类号： H04B1/7115 ,  H04B1/7117 ,  H04B2201/70701

摘要： Certain aspects of a method and system for delay matching in a rake receiver are disclosed. Aspects of one method may include compensating for a delay associated with at least one or both of the following in a rake receiver: a control channel and a data channel, prior to individual processing of received data by the data channel and individual processing of received data by the control channel. The data channel or the dedicated physical channel (DPCH) may be delayed with respect to the control channel, which may comprise, for example, the common pilot control channel (CPICH), by a particular time period.

摘要翻译： 公开了用于耙式接收机中的延迟匹配的方法和系统的某些方面。 一种方法的方面可以包括在耙式接收机中补偿与以下中的至少一个或两者相关联的延迟：控制信道和数据信道，在数据信道对接收到的数据进行单独处理之前，以及接收数据的单独处理 由控制通道。 数据信道或专用物理信道（DPCH）可以相对于可以包括例如公共导频控制信道（CPICH）的控制信道延迟特定时间段。

公开(公告)号：US20120307872A1

公开(公告)日：2012-12-06

申请号：US13588297

申请日：2012-08-17

申请人： Mark HAHM ,  Wei Luo ,  Arkady Molev-Shteiman ,  Hongwei Kong ,  Xiao-Feng Qi ,  Li Fung Chang ,  Nelson Sollenberger

发明人： Mark HAHM ,  Wei Luo ,  Arkady Molev-Shteiman ,  Hongwei Kong ,  Xiao-Feng Qi ,  Li Fung Chang ,  Nelson Sollenberger

IPC分类号： H04B1/711 ,  H04B1/10

CPC分类号： H04B1/712 ,  H04J11/0063 ,  H04J13/0044 ,  H04J13/0048

摘要： Aspects of a method and system for interference suppression in WCDMA systems may include one or more circuits that are operable to receive a plurality of multipath signals via one or more receiving antennas. A plurality of weighting factor values may be computed based on the received multipath signals. Estimated signals may be based on the weighting factor values. Residual signals may be generated based on received signals and the estimated signals. Addback signals may be generated based on the estimated signals and the residual signals. Updated estimated signals may be generated based on the addback signals and the weighting factor values. Incremental signals may be generated based on the updated estimated signals and addback signals. Updated residual signals may be generated based on the incremental signals and previous residual signals. The interference suppressed signals may be generated based on the updated residual signals and updated estimated signals.

摘要翻译： 用于WCDMA系统中的干扰抑制的方法和系统的方面可以包括可操作以经由一个或多个接收天线接收多个多径信号的一个或多个电路。 可以基于接收的多路径信号来计算多个加权因子值。 估计信号可以基于加权因子值。 可以基于接收的信号和估计的信号来产生残余信号。 可以基于估计的信号和残留信号来生成附加信号。 可以基于附加信号和加权因子值来生成更新的估计信号。 可以基于更新的估计信号和加法信号来产生增量信号。 可以基于增量信号和先前的剩余信号来生成更新的残留信号。 可以基于更新的残差信号和更新的估计信号来产生干扰抑制信号。

公开(公告)号：US20110090996A1

公开(公告)日：2011-04-21

申请号：US12582771

申请日：2009-10-21

申请人： Mark Hahm ,  Wei Luo ,  Arkady Molev-Shteiman ,  Hongwei Kong ,  Xiao-Feng Qi ,  Li Fung Chang ,  Nelson Sollenberger

发明人： Mark Hahm ,  Wei Luo ,  Arkady Molev-Shteiman ,  Hongwei Kong ,  Xiao-Feng Qi ,  Li Fung Chang ,  Nelson Sollenberger

IPC分类号： H04L1/02

CPC分类号： H04B1/712 ,  H04J11/0063 ,  H04J13/0044 ,  H04J13/0048

摘要： Aspects of a method and system for interference suppression in WCDMA systems may include one or more circuits that are operable to receive a plurality of multipath signals via one or more receiving antennas. A plurality of weighting factor values may be computed based on the received multipath signals. Estimated signals may be based on the weighting factor values. Residual signals may be generated based on received signals and the estimated signals. Addback signals may be generated based on the estimated signals and the residual signals. Updated estimated signals may be generated based on the addback signals and the weighting factor values. Incremental signals may be generated based on the updated estimated signals and addback signals. Updated residual signals may be generated based on the incremental signals and previous residual signals. The interference suppressed signals may be generated based on the updated residual signals and updated estimated signals.

摘要翻译： 用于WCDMA系统中的干扰抑制的方法和系统的方面可以包括可操作以经由一个或多个接收天线接收多个多径信号的一个或多个电路。 可以基于接收的多路径信号来计算多个加权因子值。 估计信号可以基于加权因子值。 可以基于接收的信号和估计的信号来产生残余信号。 可以基于所估计的信号和残留信号来生成附加信号。 可以基于附加信号和加权因子值来生成更新的估计信号。 可以基于更新的估计信号和加法信号来产生增量信号。 可以基于增量信号和先前的剩余信号来生成更新的残留信号。 可以基于更新的残差信号和更新的估计信号来产生干扰抑制信号。