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    Architecture for joint detection hardware accelerator
    1.
    发明授权
    Architecture for joint detection hardware accelerator 有权
    联合检测硬件加速器架构

    公开(公告)号：US07953958B2

    公开(公告)日：2011-05-31

    申请号：US11818055

    申请日：2007-06-12

    申请人： John Zijun Shen ,  Paul D. Krivacek ,  Thomas J. Barber, Jr. ,  Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic

    发明人： John Zijun Shen ,  Paul D. Krivacek ,  Thomas J. Barber, Jr. ,  Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic

    IPC分类号： G06F15/76 ,  G06F9/302

    CPC分类号： H04B1/7105 ,  H04B2201/70707 ,  H04B2201/70711

    摘要： A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

    摘要翻译： 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测加速器和主机处理器。 联合检测加速器可以包括用于存储输入数据值，中间结果和输出数据值的存储单元; 一个或多个计算单元，用于处理输入数据值和中间结果，并向存储器单元提供输出数据值; 控制器，用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。 计算单元可以包括复数乘法单元，简化复乘法累积单元和归一化浮点除法器。 存储器单元可以包括输入存储器，矩阵存储器，主存储器和输出存储器。

    Method and apparatus for joint detection
    2.
    发明授权
    Method and apparatus for joint detection 有权
    联合检测方法和装置

    公开(公告)号：US07916841B2

    公开(公告)日：2011-03-29

    申请号：US11545857

    申请日：2006-10-11

    申请人： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber, Jr. ,  John Zijun Shen

    发明人： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber, Jr. ,  John Zijun Shen

    IPC分类号： H04M1/64 ,  H04L25/49

    CPC分类号： H04B1/7105 ,  H04B2201/70711

    摘要： A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

    摘要翻译： 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测器加速器和可编程数字信号处理器（DSP）。 联合检测器加速器被配置为执行输入到联合检测器加速器的第一数据的前端处理，并输出从前端处理得到的第二数据。 联合检测器加速器还被配置为使用输入到联合检测器加速器的至少第三数据来执行后端处理。 可编程DSP耦合到联合检测器加速器，并且可编程DSP被编程为使用由联合检测器加速器输出的第二数据执行至少一个中间处理操作。 可编程DSP进一步编程为将由中间处理操作产生的第三数据输出到联合检测器加速器。

    Fixed-point implementation of a joint detector
    3.
    发明授权
    Fixed-point implementation of a joint detector 有权
    联合检测器的定点实现

    公开(公告)号：US07949925B2

    公开(公告)日：2011-05-24

    申请号：US11546062

    申请日：2006-10-11

    申请人： Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic ,  Thomas J. Barber, Jr. ,  John Zijun Shen

    发明人： Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic ,  Thomas J. Barber, Jr. ,  John Zijun Shen

    IPC分类号： H03M13/00

    CPC分类号： H04B1/7105 ,  H04B2201/70707 ,  H04L25/0224

    摘要： A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.

    摘要翻译： 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测。 联合检测系统包括联合检测器加速器，其被配置为执行对接收信号的联合检测的操作，其中联合检测包括计算关节检测变量。 该操作包括产生累加器中的值的乘法和累加运算，累加器中的值包括多个位。 联合检测器加速器被配置为选择累加器中的值的多个比特的子集，其中选择的比特的子集是可配置的。 联合检测器加速器还被配置为将位的子集存储到存储器中作为固定点表示。

    Pre-scaling of initial channel estimates in joint detection
    4.
    发明授权
    Pre-scaling of initial channel estimates in joint detection 有权
    联合检测中初始信道估计的预缩放

    公开(公告)号：US07924948B2

    公开(公告)日：2011-04-12

    申请号：US11546036

    申请日：2006-10-11

    申请人： Marko Kocic ,  Aiguo Yan ,  Lidwine Martinot ,  Thomas J. Barber, Jr. ,  John Zijun Shen

    发明人： Marko Kocic ,  Aiguo Yan ,  Lidwine Martinot ,  Thomas J. Barber, Jr. ,  John Zijun Shen

    IPC分类号： H04L27/06

    CPC分类号： H04B1/7105 ,  H04B2201/70707 ,  H04L25/0204

    摘要： A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.

    摘要翻译： 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测。 联合检测系统包括被配置为产生对应于传播信道的初始信道估计的可编程数字信号处理器（DSP），其中每个初始信道估计包括多个值。 可编程DSP还被配置为确定一个或多个初始信道估计的一个或多个预缩放因子。 预缩放因子至少部分地基于初始信道估计中的一个或多个的多个值中的至少一个值。 可编程DSP还被配置为通过预缩放因子来预缩放初始信道估计。

    Architecture for joint detection hardware accelerator
    5.
    发明申请
    Architecture for joint detection hardware accelerator 有权
    联合检测硬件加速器架构

    公开(公告)号：US20080080468A1

    公开(公告)日：2008-04-03

    申请号：US11818055

    申请日：2007-06-12

    申请人： John Zijun Shen ,  Paul D. Krivacek ,  Thomas J. Barber ,  Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic

    发明人： John Zijun Shen ,  Paul D. Krivacek ,  Thomas J. Barber ,  Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic

    IPC分类号： H04B7/216

    CPC分类号： H04B1/7105 ,  H04B2201/70707 ,  H04B2201/70711

    摘要： A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

    摘要翻译： 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测加速器和主机处理器。 联合检测加速器可以包括用于存储输入数据值，中间结果和输出数据值的存储单元; 一个或多个计算单元，用于处理输入数据值和中间结果，并向存储器单元提供输出数据值; 控制器，用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。 计算单元可以包括复数乘法单元，简化复乘法累积单元和归一化浮点除法器。 存储器单元可以包括输入存储器，矩阵存储器，主存储器和输出存储器。

    Fixed-point implementation of a joint detector
    6.
    发明申请
    Fixed-point implementation of a joint detector 有权
    联合检测器的定点实现

    公开(公告)号：US20080089448A1

    公开(公告)日：2008-04-17

    申请号：US11546062

    申请日：2006-10-11

    申请人： Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic ,  Thomas J. Barber ,  John Zijun Shen

    发明人： Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic ,  Thomas J. Barber ,  John Zijun Shen

    IPC分类号： H04L27/06

    CPC分类号： H04B1/7105 ,  H04B2201/70707 ,  H04L25/0224

    摘要： A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.

    摘要翻译： 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测。 联合检测系统包括联合检测器加速器，其被配置为执行对接收信号的联合检测的操作，其中联合检测包括计算关节检测变量。 该操作包括产生累加器中的值的乘法和累加运算，累加器中的值包括多个位。 联合检测器加速器被配置为选择累加器中的值的多个比特的子集，其中选择的比特的子集是可配置的。 联合检测器加速器还被配置为将位的子集存储到存储器中作为固定点表示。

    Pre-scaling of initial channel estimates in joint detection
    7.
    发明申请
    Pre-scaling of initial channel estimates in joint detection 有权
    联合检测中初始信道估计的预缩放

    公开(公告)号：US20080080645A1

    公开(公告)日：2008-04-03

    申请号：US11546036

    申请日：2006-10-11

    申请人： Marko Kocic ,  Aiguo Yan ,  Lidwine Martinot ,  Thomas J. Barber ,  John Zijun Shen

    发明人： Marko Kocic ,  Aiguo Yan ,  Lidwine Martinot ,  Thomas J. Barber ,  John Zijun Shen

    IPC分类号： H04L27/06

    CPC分类号： H04B1/7105 ,  H04B2201/70707 ,  H04L25/0204

    摘要： A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.

    摘要翻译： 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测。 联合检测系统包括被配置为产生对应于传播信道的初始信道估计的可编程数字信号处理器（DSP），其中每个初始信道估计包括多个值。 可编程DSP还被配置为确定一个或多个初始信道估计的一个或多个预缩放因子。 预缩放因子至少部分地基于初始信道估计中的一个或多个的多个值中的至少一个值。 可编程DSP还被配置为通过预缩放因子来预缩放初始信道估计。

    Method and apparatus for joint detection
    8.
    发明申请
    Method and apparatus for joint detection 有权
    联合检测方法和装置

    公开(公告)号：US20080080638A1

    公开(公告)日：2008-04-03

    申请号：US11545857

    申请日：2006-10-11

    申请人： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber ,  John Zijun Shen

    发明人： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber ,  John Zijun Shen

    IPC分类号： H04L25/49

    CPC分类号： H04B1/7105 ,  H04B2201/70711

    摘要： A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

    摘要翻译： 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测器加速器和可编程数字信号处理器（DSP）。 联合检测器加速器被配置为执行输入到联合检测器加速器的第一数据的前端处理，并输出从前端处理得到的第二数据。 联合检测器加速器还被配置为使用输入到联合检测器加速器的至少第三数据来执行后端处理。 可编程DSP耦合到联合检测器加速器，并且可编程DSP被编程为使用由联合检测器加速器输出的第二数据执行至少一个中间处理操作。 可编程DSP进一步编程为将由中间处理操作产生的第三数据输出到联合检测器加速器。