公开(公告)号：US5880009A

公开(公告)日：1999-03-09

申请号：US812426

申请日：1997-03-06

Applicant: Lin-Song Wang

Inventor： Lin-Song Wang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76221

Abstract: A method for forming oxides on buried N.sup.+ -type regions in a memory cell fabrication process, suitable for forming oxides on the bury N.sup.+ -type regions before self-aligned MOS device etching, comprises: (1) implanting a high concentration of impurity into the buried N.sup.+ -type regions; (2) annealing the chip; and (3) executing a dry oxide process and then a wet oxidation process to the chip, thereby preventing damage to the edges of buried N.sup.+ -type regions caused by non-uniform thickness of oxides on buried regions during self-aligned MOS etching and resolving the problem of non-uniform oxides on buried N.sup.+ -type regions.

Abstract translation: 在自对准MOS器件蚀刻之前，适用于在掩埋N +型区域上形成氧化物的存储单元制造工艺中在掩埋N +型区域上形成氧化物的方法包括：（1）将高浓度的杂质注入到 埋N +型区; （2）芯片退火; 和（3）对芯片执行干式氧化处理，然后进行湿式氧化处理，从而防止在自对准MOS蚀刻和分解过程中由掩埋区域上的氧化物的不均匀厚度引起的掩埋的N +型区域的边缘的损坏 埋藏N +型区域不均匀氧化物的问题。

公开(公告)号：US5978274A

公开(公告)日：1999-11-02

申请号：US128217

申请日：1998-08-03

Applicant: Lin-Song Wang

Inventor： Lin-Song Wang

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14

Abstract: A method of erasing a split gate flash memory cell is provided, which can be used in the operation of a split gate flash memory cell to increase the number of its rewritable cycles. The improvement is remarkable especially for flash memory cells while its floating gate channel length is under a 0.4 .mu.m-feature size. The erasing method includes the steps of: (i) applying a negative voltage to the control gate and applying a positive voltage to the drain to form a forward electrical field between the drain and the control gate; and (ii) applying a positive voltage to the source to reduce a voltage difference between the drain and the source, so that electrons in the floating gate are discharged under the effect of the forward electrical field generated by the Fowler-Nordheim tunneling effect, and hot holes can be reduced and prevented from accumulating in a tunnel oxide between the floating gate and the drain, thereby erasing the split-gate flash memory cell, and increasing the number of rewritable cycles for the flash memory cell.

Abstract translation: 提供了一种擦除分离栅闪存单元的方法，其可用于分割栅闪存单元的操作以增加其可重写循环的数量。 特别是对于闪存单元而言，其浮动栅极通道长度小于0.4μm特征尺寸的改进是显着的。 擦除方法包括以下步骤：（i）向控制栅极施加负电压并向漏极施加正电压以在漏极和控制栅极之间形成正向电场; 并且（ii）向源极施加正电压以减小漏极和源极之间的电压差，使得浮置栅极中的电子在由Fowler-Nordheim隧道效应产生的正向电场的作用下被放电，以及 可以减少热孔并且防止在浮置栅极和漏极之间的隧道氧化物中积聚，从而擦除分流栅极闪存单元，并增加闪存单元的可重写周期数。

公开(公告)号：US5856223A

公开(公告)日：1999-01-05

申请号：US859968

申请日：1997-05-21

Applicant: Lin-Song Wang

Inventor： Lin-Song Wang

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: A method for manufacturing self-aligned split-gate flash memory cells wherein the split-gate structure is formed by a self-aligned approach, so that the length of a channel can be precisely controlled. Furthermore, sources and drains are formed separately by executing different implantations, so that the dopant parameters of the sources and drains can be changed, based on desired and possibly different characteristics.

Abstract translation: 一种用于制造自对准分裂栅极闪存单元的方法，其中分离栅结构通过自对准方法形成，使得可以精确地控制通道的长度。 此外，通过执行不同的注入来分别形成源极和漏极，从而可以基于期望的和可能不同的特性来改变源极和漏极的掺杂剂参数。