公开(公告)号：US09811113B2

公开(公告)日：2017-11-07

申请号：US15208482

申请日：2016-07-12

申请人： Linear Technology Corporation

发明人： Richard William Ezell ,  Eric Wright Mumper

IPC分类号： G06F1/12 ,  H03L7/23 ,  G06F1/10

CPC分类号： G06F1/12 ,  G06F1/10 ,  H03L7/23

摘要： A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.

公开(公告)号：US20170134031A1

公开(公告)日：2017-05-11

申请号：US15208482

申请日：2016-07-12

申请人： Linear Technology Corporation

发明人： Richard William Ezell ,  Eric Wright Mumper

IPC分类号： H03L7/23

CPC分类号： G06F1/12 ,  G06F1/10 ,  H03L7/23

摘要： A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.