公开(公告)号：US20160182056A1

公开(公告)日：2016-06-23

申请号：US14574893

申请日：2014-12-18

Applicant: Linear Technology Corporation

Inventor： Eric Wright Mumper ,  Jan-Michael Stevenson

IPC: H03K21/02 ,  H03K19/173

CPC classification number: H03K21/026 ,  H03K19/1737

Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.

Abstract translation: 时钟分频电路接收给定频率的延迟值，同步信号和外部时钟信号。 时钟分频电路包括：（a）解码电路，接收延迟值并提供一组初始计数值; （b）一个或多个计数器，每个接收从外部时钟信号导出的输入时钟信号，并提供具有给定频率的一小部分的频率的分频输出信号，并且每个接收相应的一个初始计数值，并且其中，随后 为了检测同步信号中的转换，每个计数器在由对应的初始计数值表示的时间段之后提供分频输出信号中的转换; 和（c）由同步信号复位的同步电路，同步电路提供门限信号，使得能够在初始计数值到期之后输出分频输出信号。 一个或多个计数器可以级联。

公开(公告)号：US09397668B2

公开(公告)日：2016-07-19

申请号：US14574893

申请日：2014-12-18

Applicant: Linear Technology Corporation

Inventor： Eric Wright Mumper ,  Jan-Michael Stevenson

IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K21/02 ,  H03K19/173

CPC classification number: H03K21/026 ,  H03K19/1737

Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.

Abstract translation: 时钟分频电路接收给定频率的延迟值，同步信号和外部时钟信号。 时钟分频电路包括：（a）解码电路，接收延迟值并提供一组初始计数值; （b）一个或多个计数器，每个接收从外部时钟信号导出的输入时钟信号，并提供具有给定频率的一小部分的频率的分频输出信号，并且每个接收相应的一个初始计数值，并且其中，随后 为了检测同步信号中的转换，每个计数器在由对应的初始计数值表示的时间段之后提供分频输出信号中的转换; 和（c）由同步信号复位的同步电路，同步电路提供门限信号，使得能够在初始计数值到期之后输出分频输出信号。 一个或多个计数器可以级联。

公开(公告)号：US09811113B2

公开(公告)日：2017-11-07

申请号：US15208482

申请日：2016-07-12

Applicant: Linear Technology Corporation

Inventor： Richard William Ezell ,  Eric Wright Mumper

IPC: G06F1/12 ,  H03L7/23 ,  G06F1/10

CPC classification number: G06F1/12 ,  G06F1/10 ,  H03L7/23

Abstract: A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.

公开(公告)号：US20170134031A1

公开(公告)日：2017-05-11

申请号：US15208482

申请日：2016-07-12

Applicant: Linear Technology Corporation

Inventor： Richard William Ezell ,  Eric Wright Mumper

IPC: H03L7/23

CPC classification number: G06F1/12 ,  G06F1/10 ,  H03L7/23

Abstract: A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.