公开(公告)号：US20240431110A1

公开(公告)日：2024-12-26

申请号：US18827561

申请日：2024-09-06

Applicant: Lodestar Licensing Group LLC

Inventor： Aaron S. Yip

IPC: H10B43/27 ,  G11C11/56 ,  G11C16/08 ,  G11C16/24 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H10B41/27

Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.

公开(公告)号：US20240404976A1

公开(公告)日：2024-12-05

申请号：US18805777

申请日：2024-08-15

Applicant: Lodestar Licensing Group LLC

Inventor： Akira Goda ,  Kunal R. Parekh ,  Aaron S. Yip

IPC: H01L23/00 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.