公开(公告)号：US20070113064A1

公开(公告)日：2007-05-17

申请号：US11281115

申请日：2005-11-17

申请人： Longyin Wei ,  Iue-Shuenn Chen ,  Yuqian Wong

发明人： Longyin Wei ,  Iue-Shuenn Chen ,  Yuqian Wong

IPC分类号： G06F15/177

CPC分类号： G06F21/575

摘要： Certain embodiments of a method and system for secure code patching may comprise modifying execution of boot code in an on-chip ROM during booting of the chip. Patch code resident in memory internal to the chip may be used to modify execution of the boot code. The address bus may be monitored for boot code addresses that match break addresses stored within the chip. If a match occurs, a start address that corresponds to the matched break address may be used to jump to a portion of the patch code. Accordingly, there may be a break in execution of the boot code, and a portion of the patch code may be executed. An instruction at the end of the portion of the patch code that is executed may be used to return to the boot code.

摘要翻译： 用于安全代码修补的方法和系统的某些实施例可以包括在引导芯片期间修改在片上ROM中引导代码的执行。 驻留在芯片内部的存储器中的补丁代码可用于修改引导代码的执行。 地址总线可以被监视与芯片中存储的断点地址匹配的引导代码地址。 如果发生匹配，则可以使用与匹配的中断地址对应的起始地址来跳转到补丁码的一部分。 因此，引导代码的执行可能会中断，并且可以执行补丁代码的一部分。 执行补丁代码部分末尾的指令可用于返回引导代码。

公开(公告)号：US20060040632A1

公开(公告)日：2006-02-23

申请号：US11257945

申请日：2005-10-25

申请人： Mitchell Buznitsky ,  Yuqian Wong ,  Daniel Bozich ,  Brima Ibrahim

发明人： Mitchell Buznitsky ,  Yuqian Wong ,  Daniel Bozich ,  Brima Ibrahim

IPC分类号： H04B1/06 ,  H04B7/00

CPC分类号： H03L7/18 ,  G06F1/06 ,  G06F1/12 ,  H03L7/1974

摘要： Determination and processing for fractional-N programming values. The present invention is operable to receive a clock signal (CLK) and to transform that CLK into a new CLK, when necessary, for use by various circuitries within a system. The present invention is operable to generate two different CLKs for use by a radio frequency (RF) circuitry and a baseband processing circuitry in certain embodiments. The present invention employs a measurement circuitry and to characterize a first CLK and uses a fractional-N synthesizer to perform any necessary processing to generate the one or more CLKs to the other CLKs within the system. The first CLK may be received from an external source or it may be generated internally; in either case, the present invention is able to modify the CLK into another CLK for use by other circuitries within the system or for use by another external device.

公开(公告)号：US20070260954A1

公开(公告)日：2007-11-08

申请号：US11418588

申请日：2006-05-04

申请人： Yuqian Wong

发明人： Yuqian Wong

IPC分类号： G01R31/28

CPC分类号： G01R31/318575

摘要： An integrated circuit with low-power built-in self-test logic (“IC-LPBIST”) is disclosed. The IC-LPBIST may include combinational logic and a loading circuit enabled to load a shift test pattern of data into the loading circuit without powering the combinational logic of the IC-LPBIST, wherein the shift test pattern of data is configured to test the combinational logic for logical faults.

摘要翻译： 公开了具有低功率内置自检逻辑（“IC-LPBIST”）的集成电路。 IC-LPBIST可以包括组合逻辑和加载电路，其能够将数据的移位测试模式加载到加载电路中，而不对IC-LPBIST的组合逻辑进行供电，其中数据的移位测试模式被配置为测试组合逻辑 用于逻辑故障。

公开(公告)号：US20060020840A1

公开(公告)日：2006-01-26

申请号：US10932491

申请日：2004-09-02

申请人： Yuqian Wong ,  Yuan Zhuang

发明人： Yuqian Wong ,  Yuan Zhuang

IPC分类号： H04L7/00

CPC分类号： G06F9/4825 ,  G04G15/006 ,  H04L7/10 ,  Y02D10/24

摘要： Timing vectors are used to pass execution of time-dependent operations from firmware/software to a hardware component (e.g., a state machine). These vectors may be stored as a vector table in a data memory that is accessible by both the firmware/software and the hardware component. Based on the processing being performed in the system, the firmware/software will determine that one or more operations will need to be performed at a certain time. The firmware/software stores a reference to that time and a reference to the operation(s) in a vector. The hardware component continually monitors time in the system. In addition, the hardware component will monitor each vector to determine whether the current time matches the time associated with a given vector. When there is match, the hardware component causes the operation(s) associated with the vector to be performed. The system also may perform different operations at a given time depending on the operating condition (e.g., state) of the system.

摘要翻译： 使用定时向量将来自固件/软件的时间相关操作的执行传递到硬件组件（例如，状态机）。 这些向量可以作为向量表存储在可由固件/软件和硬件组件访问的数据存储器中。 基于在系统中执行的处理，固件/软件将确定需要在特定时间执行一个或多个操作。 固件/软件存储对该时间的引用和对矢量中的操作的引用。 硬件组件会持续监控系统中的时间。 此外，硬件组件将监视每个向量以确定当前时间是否与给定向量相关联的时间匹配。 当匹配时，硬件组件导致执行与向量相关联的操作。 系统还可以根据系统的操作条件（例如状态）在给定时间执行不同的操作。

公开(公告)号：US20090113175A1

公开(公告)日：2009-04-30

申请号：US11980026

申请日：2007-10-30

申请人： Yuqian Wong ,  Junfeng Wang

发明人： Yuqian Wong ,  Junfeng Wang

IPC分类号： G06F9/30 ,  G06F15/76

CPC分类号： G06F9/322 ,  G06F9/328

摘要： In one embodiment, a processor architecture for concurrently fetching data and patched instructions includes a microprocessor, an instruction patch, a dedicated instruction memory, a patch memory, and a dedicated data memory. The instruction patch is coupled to the microprocessor by an instruction bus, and is also coupled to the dedicated instruction memory and the patch memory. The patch memory and the dedicated data memory are coupled to the microprocessor by a data bus separate from the instruction bus. In one embodiment, the instruction patch has a number of comparators that can be individually enabled by respective enable signals. Each comparator that is enabled compares every bit on an instruction address with a corresponding bit of a patched instruction address to detect a patch condition. When a patch condition is detected, patched instructions are fetched from the patch memory, while the microprocessor can concurrently fetch data from the dedicated data memory.

摘要翻译： 在一个实施例中，用于同时提取数据和修补指令的处理器架构包括微处理器，指令补丁，专用指令存储器，补丁存储器和专用数据存储器。 指令补丁通过指令总线耦合到微处理器，并且还耦合到专用指令存储器和补丁存储器。 补丁存储器和专用数据存储器通过与指令总线分离的数据总线耦合到微处理器。 在一个实施例中，指令补丁具有多个比较器，其可以由相应的使能信号单独使能。 启用的每个比较器将指令地址上的每个位与修补指令地址的相应位进行比较，以检测补丁条件。 当检测到补丁条件时，从补丁存储器中取出补丁指令，而微处理器可以从专用数据存储器同时提取数据。

公开(公告)号：US20070240001A1

公开(公告)日：2007-10-11

申请号：US11715211

申请日：2007-03-07

申请人： Masood Syed ,  Yuqian Wong ,  Brima Ibrahim ,  Mitchell Buznitsky

发明人： Masood Syed ,  Yuqian Wong ,  Brima Ibrahim ,  Mitchell Buznitsky

IPC分类号： G06F1/26

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  Y02D10/171

摘要： An embedded processor system including at least one gated power unit including an internal ROM and a power controller that provides one or more gated power signals to selectively provide power to each gated power unit. The power controller provides a gated clock signal to the embedded processor to selectively control power consumption of the processor. The power controller powers down each gated power unit after freezing the processor and then powers up each gated power unit before reactivating the processor. The embedded processor system may include isolation circuitry, such as clamp circuitry or the like, that is operative to minimize current flow into each gated power unit when powered down. The gated power units may include a static function. The ROM of an embedded ROM-based microprocessor system is powered down when the microprocessor is idle to reduce or otherwise eliminate intrinsic leakage.