Memory cell with non-destructive one-time programming
    3.
    发明申请
    Memory cell with non-destructive one-time programming 有权
    具有非破坏性一次性编程的存储单元

    公开(公告)号:US20050122759A1

    公开(公告)日:2005-06-09

    申请号:US10504273

    申请日:2003-02-11

    IPC分类号: G11C16/22 G11C17/14 G11C17/00

    CPC分类号: G11C17/14 G11C16/22

    摘要: The invention relates to a one-time programmable memory cell and the programming method thereof. Thc invention comprises a programming transistor (MN) which is disposed in series with a polycrystalline silicon programming resistor (Rp) forming the memory element. According to the invention, the programming is non destructive with respect to the polycrystalline silicon resistor.

    摘要翻译: 本发明涉及一次性可编程存储单元及其编程方法。 本发明包括与形成存储元件的多晶硅编程电阻器(Rp)串联布置的编程晶体管(MN)。 根据本发明,编程对于多晶硅电阻器是非破坏性的。

    Extraction of a binary code based on physical parameters of an integrated circuit
    4.
    发明授权
    Extraction of a binary code based on physical parameters of an integrated circuit 有权
    基于集成电路的物理参数提取二进制代码

    公开(公告)号:US06836430B2

    公开(公告)日:2004-12-28

    申请号:US10364848

    申请日:2003-02-11

    IPC分类号: G11C1604

    CPC分类号: G11C14/00 H03K3/356008

    摘要: An extraction method and an integrated cell for extracting a binary value based on a propagation of an edge of a triggering signal in two electric paths, including across two voltage supply terminals: two parallel branches each including, in series, a resistor for differentiating the electric paths; a read transistor, the junction point of the resistor and of the read transistor of each branch defining an output terminal of the cell, and the gate of the read transistor of each branch being connected to the output terminal of the other branch; and a selection transistor.

    摘要翻译: 一种提取方法和集成单元,用于基于两个电路中的触发信号的边缘的传播提取二进制值,包括两个电压源端:两个并联支路,每个并联支路分别包括用于区分电 路径 读取晶体管,每个分支的电阻器和读取晶体管的结点限定单元的输出端子,并且每个分支的读取晶体管的栅极连接到另一个分支的输出端子; 和选择晶体管。

    One-time programmable memory cell
    7.
    发明申请
    One-time programmable memory cell 审中-公开
    一次性可编程存储单元

    公开(公告)号:US20050162892A1

    公开(公告)日:2005-07-28

    申请号:US10504203

    申请日:2003-02-11

    CPC分类号: G11C17/14 G11C16/22

    摘要: The invention relates to a memory cell with a binary value consisting of two parallel branches. Each of said branches comprises: at least one polycrystalline silicon programming resistor (Rp1, Rp2), which is connected between a first supply terminal (1) and a point or terminal for the differential reading (4, 6) of the memory cell state; and at least one first switch (MNP1, MNP2) which, during programming, connects one of said read terminals to a second supply terminal (2).

    摘要翻译: 本发明涉及具有由两个平行分支组成的二进制值的存储单元。 每个所述分支包括:至少一个多晶硅编程电阻器(Rp 1,Rp 2),其连接在第一电源端子(1)和用于存储器单元的差分读取(4,6)的点或端子之间 州; 以及在编程期间将所述读取终端中的一个连接到第二电源端子(2)的至少一个第一开关(MNP 1,MNP 2)。