公开(公告)号：US06353644B1

公开(公告)日：2002-03-05

申请号：US09303730

申请日：1999-05-03

申请人： Lujing Cai ,  Weimin Liu ,  Xiao Liu ,  Wenye Yang

发明人： Lujing Cai ,  Weimin Liu ,  Xiao Liu ,  Wenye Yang

IPC分类号： H04B110

CPC分类号： H04L25/03038 ,  H04L2025/03414 ,  H04L2025/03477

摘要： Disclosed is a system and method for signal conditioning and equalization in the time domain, preferably in a discrete multi-tone (DMT) modem. The system preferably includes a processor operating according to operating logic stored on a memory although a dedicated logical circuit may be employed. The operating logic includes logic executing the function of a low pass filter having a predetermined cutoff frequency configured to process a digitized data signal having a first sample rate f0, producing a filtered data signal at a second sample rate f1. The operating logic further includes logic which executes the function of a time domain equalizer, the time domain equalizer being configured to process the filtered signal to shorten the impulse response of the channel while at the same time, the time domain equalizer down-samples the filtered signal from the second sample rate f1, to a third sample rate f2 for further processing in the frequency domain.

摘要翻译： 公开了一种在时域中信号调节和均衡的系统和方法，优选地在离散多音调（DMT）调制解调器中。 该系统优选地包括根据存储在存储器上的操作逻辑操作的处理器，尽管可以采用专用逻辑电路。 操作逻辑包括执行具有预定截止频率的低通滤波器的功能的逻辑，所述低通滤波器被配置为处理具有第一采样率f0的数字化数据信号，以第二采样率f1产生滤波数据信号。 操作逻辑还包括执行时域均衡器的功能的逻辑，时域均衡器被配置为处理滤波信号以缩短信道的脉冲响应，同时时域均衡器对滤波后的 信号从第二采样率f1到第三采样率f2，用于在频域中进一步处理。

公开(公告)号：US06421377B1

公开(公告)日：2002-07-16

申请号：US09164552

申请日：1998-10-01

申请人： Ehud Langberg ,  Xueming Lin ,  Weimin Liu ,  Wenye Yang

发明人： Ehud Langberg ,  Xueming Lin ,  Weimin Liu ,  Wenye Yang

IPC分类号： H04B138

CPC分类号： H04B3/23 ,  H04L27/2647

摘要： The present invention generally relates to echo cancellation over an asymmetric transmission and receiving spectra. An apparatus is provided having a transmit path and a receive path, with an adaptive echo canceler disposed therebetween, for communicating data within a first bandwidth and a second bandwidth respectively. A first decimator is disposed between the transmit path and the echo canceler circuit and filters an incoming signal having a first sampling rate and emits a signal output at a second, reduced sampling rate. A second decimator is disposed along said receive path and filters an incoming signal and emits a signal output at a reduced sampling rate. An adder is disposed to subtract the output of the adaptive echo canceler from output of the second decimator to generate a received signal that is substantially free of echo.

摘要翻译： 本发明一般涉及不对称传输和接收光谱的回波消除。 提供一种具有发送路径和接收路径的装置，其间设置有自适应回波消除器，用于分别在第一带宽和第二带宽内传送数据。 第一抽取器设置在发射路径和回波抵消器电路之间，并且对具有第一采样率的输入信号进行滤波，并以第二次降低的采样率发射信号输出。 沿着所述接收路径设置第二抽取器，并且对输入信号进行滤波并以降低的采样率发射信号输出。 设置加法器以从第二抽取器的输出中减去自适应回波消除器的输出，以产生基本上没有回波的接收信号。

公开(公告)号：US20080046497A1

公开(公告)日：2008-02-21

申请号：US11840547

申请日：2007-08-17

申请人： Yue-Peng Zheng ,  Ehud Langberg ,  Wenye Yang

发明人： Yue-Peng Zheng ,  Ehud Langberg ,  Wenye Yang

IPC分类号： G06F7/38 ,  G06F1/16

CPC分类号： G06F7/5324 ,  G06F2207/382

摘要： Systems and methods for a memory structure are described for increasing the throughput of double precision operations. Broadly, the present invention utilizes a novel memory system to process double precision data in a single memory access. In accordance with one embodiment, a method for increasing throughput of arithmetic operations on double precision data by reducing the number of memory accesses comprising: retrieving a double precision value from a memory, wherein the double precision value is comprised of a high word and a low word, wherein the double precision value is retrieved in a single memory access; selecting a word within the double precision value, wherein the portion selected is a single precision value; multiplying the word with a single precision operand to generate a single precision product; adding the product to a double precision operand to produce a double precision result; and forwarding the double precision result back to memory for storage.

摘要翻译： 描述了用于增加双精度操作的吞吐量的存储器结构的系统和方法。 广义上，本发明利用一种新颖的存储器系统来处理单个存储器访问中的双精度数据。 根据一个实施例，一种用于通过减少存储器访问的数量来增加对双精度数据的算术运算的吞吐量的方法，包括：从存储器检索双精度值，其中双精度值由高字和低字组成 单词，其中在单个存储器访问中检索所述双精度值; 选择双精度值内的单词，其中所选择的部分是单精度值; 将单词与单精度操作数相乘以生成单精度乘积; 将产品添加到双精度操作数以产生双精度结果; 并将双精度结果转发回存储器进行存储。