公开(公告)号：US20210004030A1

公开(公告)日：2021-01-07

申请号：US16921842

申请日：2020-07-06

申请人： M31 TECHNOLOGY CORPORATION

发明人： CHING-HSIANG CHANG ,  CHIH-CHIEH YAO ,  CHUN-HSIANG LAI

IPC分类号： G05F1/46 ,  H03K3/037 ,  H03K19/20 ,  H03K5/00

摘要： A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

公开(公告)号：US20230135657A1

公开(公告)日：2023-05-04

申请号：US18146789

申请日：2022-12-27

申请人： M31 TECHNOLOGY CORPORATION

发明人： CHING-HSIANG CHANG ,  CHIH-CHIEH YAO ,  CHUN-HSIANG LAI

IPC分类号： G05F1/46 ,  H03K3/037 ,  H03K5/00 ,  H03K19/20

摘要： A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.