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    IMPEDANCE CALIBRATION CIRCUIT AND METHOD
    1.
    发明公开
    IMPEDANCE CALIBRATION CIRCUIT AND METHOD 审中-公开

    公开(公告)号：US20240305275A1

    公开(公告)日：2024-09-12

    申请号：US18182172

    申请日：2023-03-10

    Applicant: M31 TECHNOLOGY CORPORATION

    Inventor： MING-YEN TSAI ,  TZE-HSIANG CHAO

    IPC: H03H11/28 ,  G11C7/10 ,  H03K5/24

    CPC classification number: H03H11/28 ,  G11C7/1048 ,  H03K5/24 ,  G11C2207/2254

    Abstract: An impedance calibration circuit includes a variable impedance circuit, a detection circuit and a control circuit. The variable impedance circuit includes conduction paths connected in parallel between an output terminal and a supply terminal coupled to a first supply voltage. The variable impedance circuit is configured to adjust an impedance at the output terminal by enabling one or more of the conduction paths according to a calibration code. The detection circuit is configured to detect a change in impedance of the conduction paths by applying a second supply voltage to a reference terminal through a detection path, and accordingly generate an input voltage at the reference terminal. An electric potential of the second supply voltage is equal to an electric potential of the first supply voltage. The control circuit is configured to compare the input voltage with reference voltages to generate the calibration code.

    INTEGRATED CIRCUIT HAVING LANES INTERCHANGEABLE BETWEEN CLOCK AND DATA LANES IN CLOCK FORWARD INTERFACE RECEIVER
    5.
    发明申请
    INTEGRATED CIRCUIT HAVING LANES INTERCHANGEABLE BETWEEN CLOCK AND DATA LANES IN CLOCK FORWARD INTERFACE RECEIVER 有权

    公开(公告)号：US20210303490A1

    公开(公告)日：2021-09-30

    申请号：US17343704

    申请日：2021-06-09

    Applicant: M31 TECHNOLOGY CORPORATION

    Inventor： YUEH-CHUAN LU ,  CHING-HSIANG CHANG

    IPC: G06F13/20 ,  G06F1/10

    Abstract: An integrated circuit in a transmitter includes a multilane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively, (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier,

    POWER MANAGEMENT CIRCUIT AND METHOD FOR INTEGRATED CIRCUIT HAVING MULTIPLE POWER DOMAINS
    6.
    发明申请
    POWER MANAGEMENT CIRCUIT AND METHOD FOR INTEGRATED CIRCUIT HAVING MULTIPLE POWER DOMAINS 有权

    公开(公告)号：US20210004030A1

    公开(公告)日：2021-01-07

    申请号：US16921842

    申请日：2020-07-06

    Applicant: M31 TECHNOLOGY CORPORATION

    Inventor： CHING-HSIANG CHANG ,  CHIH-CHIEH YAO ,  CHUN-HSIANG LAI

    IPC: G05F1/46 ,  H03K3/037 ,  H03K19/20 ,  H03K5/00

    Abstract: A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

    Memory device capable of releasing stress voltage
    7.
    发明授权
    Memory device capable of releasing stress voltage 有权

    公开(公告)号：US10692568B2

    公开(公告)日：2020-06-23

    申请号：US16130807

    申请日：2018-09-13

    Applicant: M31 TECHNOLOGY CORPORATION

    Inventor： Shyh-Chyi Yang ,  Wei-Chiang Shih

    IPC: G11C11/419 ,  G11C7/10 ,  G11C11/412 ,  G11C11/413

    Abstract: A memory device includes: at least one memory cell; a bit line connected to the at least one memory cell; a write controller; a write driver receiving a logic signal from an output terminal of the write controller, and driving the bit line based on the logic signal; a negative voltage generator generating a reference voltage for receipt by a ground terminal of the write driver; and a protector connected to one of a power terminal and the output terminal of the write controller. The protector is capable of releasing stress voltage of the write driver.

    CLOCK GENERATION CIRCUIT AND ASSOCIATED CIRCUITRY
    8.
    发明申请
    CLOCK GENERATION CIRCUIT AND ASSOCIATED CIRCUITRY 审中-公开

    公开(公告)号：US20200014389A1

    公开(公告)日：2020-01-09

    申请号：US16028845

    申请日：2018-07-06

    Applicant: M31 TECHNOLOGY CORPORATION

    Inventor： YU HSIANG CHANG ,  CHING-HSIANG CHANG

    IPC: H03L7/07

    Abstract: A clock generation circuit arranged in a first system is disclosed. The clock generation circuit includes: a first dual-mode PLL, arranged for generating a first output clock in an integer-N mode or a fractional-N mode selectively, the first output clock being generated based on a first reference clock; and a second dual-mode PLL, arranged for generating a second output clock in an integer-N mode or a fractional-N mode selectively, the second output clock being generated based on the first output clock or a second reference clock selectively. Associated circuitries are also disclosed.

    Transmitter and a post-cursor compensation system thereof
    9.
    发明授权
    Transmitter and a post-cursor compensation system thereof 有权

    公开(公告)号：US10263715B1

    公开(公告)日：2019-04-16

    申请号：US15896071

    申请日：2018-02-14

    Applicant: M31 Technology Corporation

    Inventor： Shuo-Ting Kao

    IPC: H04B17/15 ,  H04B1/04

    Abstract: A post-cursor compensation system includes a state detector that receives a signal on a data line to detect a predefined state, and accordingly generates a clear control signal; a synchronization detector that receives the signal on the data line and the clear control signal to detect at least one synchronization state, and accordingly generates a trigger signal; and a compensation generator that receives the trigger signal and accordingly generates a compensation signal.

    SRAM MODULE AND WRITING CONTROL METHOD THEREOF
    10.
    发明申请
    SRAM MODULE AND WRITING CONTROL METHOD THEREOF 审中-公开

    公开(公告)号：US20180102165A1

    公开(公告)日：2018-04-12

    申请号：US15836922

    申请日：2017-12-11

    Applicant: M31 Technology Corporation

    Inventor： NAN-CHUN LIEN ,  DAVID C. YU

    IPC: G11C11/419

    CPC classification number: G11C11/419

    Abstract: A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.

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