公开(公告)号：US20250105789A1

公开(公告)日：2025-03-27

申请号：US18371217

申请日：2023-09-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shang-Chi YANG ,  Tung-Yu LI ,  Jian-Syu LIN

IPC: H03F1/02 ,  H03F3/45

Abstract: A differential amplifier includes an input pair of transistors with a source-side resistor circuit, having a transistor biased in a triode region, and a current source. The resistor circuit in combination with a capacitance, causes source degeneration in the amplifier. The source side resistor circuit includes a first MOS transistor having a first channel terminal connected to the source of a first transistor in the differential pair, and a second channel terminal connected to the bulk terminal, and a second MOS transistor having a first channel terminal connected to the source of a second transistor in the differential pair, and a second channel terminal connected to the bulk terminal. A bias circuit biases the first MOS transistor and the second MOS transistor in a triode region. The resistance of the source-side resistor circuit and the gain of the transistors in the differential amplifier can track across process corners.

公开(公告)号：US20240283679A1

公开(公告)日：2024-08-22

申请号：US18111793

申请日：2023-02-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Jian-Syu LIN ,  Shang-Chi YANG ,  Tung-Yu LI

IPC: H04L25/03

CPC classification number: H04L25/03885

Abstract: A continuous time linear equalizer (CTLE) circuit is provided. The CTLE circuit can include a differential pair of first and second transistors, the first and second transistors having drains connected through first and second drain resistors to a drain-side supply voltage node, and sources connected together by a source resistor and connected to one or more current sources, the first transistor in the differential pair having a gate connected to a reference voltage, and the second transistor in the differential pair having a gate connected to an input voltage, the drains of the first and second transistors providing a differential pair of signals as an output voltage, a first coupling capacitor connected between the source of the first transistor and the input voltage, and a second coupling capacitor connected to the source of the second transistor.

公开(公告)号：US20230056520A1

公开(公告)日：2023-02-23

申请号：US17405812

申请日：2021-08-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Su-Chueh LO ,  Jian-Syu LIN ,  Yi-Fan CHANG

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device that has a first layer including conductive material, a bond wire coupled to an upper surface of the first layer, and a second layer including conductive material underneath the first layer. One or more interconnects couple the second layer to the first layer. In an example, the second layer has a plurality of discontinuous sections that includes (i) a connected section coupled to the one or more interconnects and (ii) one or more floating sections that are at least in part surrounded by the connected section, where the one or more floating sections are electrically floating and isolated from the connected section. The semiconductor device also includes an under-pad circuit on a substrate underneath the second layer, the under-pad circuit to transmit signals to one or more components external to the semiconductor device though the first layer.