公开(公告)号：US20240274170A1

公开(公告)日：2024-08-15

申请号：US18109455

申请日：2023-02-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung HUNG ,  Ken-Hui CHEN ,  Shang-Chi YANG ,  Tung-Yu LI

IPC: G11C7/12 ,  G06F7/544 ,  G11C8/08

CPC classification number: G11C7/12 ,  G06F7/5443 ,  G11C8/08

Abstract: Compute-in-memory CIM operations using signed bits produce signed outputs. A circuit for CIM operations comprises an array of memory cells arranged in columns and rows, memory cells in columns connected to corresponding bit lines, and memory cells in rows connected to corresponding word lines. The array is programmable to store signed weights in sets of memory cells, the sets being operatively coupled with a corresponding pair of bit lines and a corresponding pair of word lines. Word line drivers are configured to drive true and complement voltages representing signed inputs on respective word lines in selected pairs of word lines. Sensing circuits are configured to sense differences between first and second currents on respective bit lines in selected pairs of bit lines and to produce signed outputs for the selected pairs of bit lines as a function of the difference.

公开(公告)号：US20240283679A1

公开(公告)日：2024-08-22

申请号：US18111793

申请日：2023-02-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Jian-Syu LIN ,  Shang-Chi YANG ,  Tung-Yu LI

IPC: H04L25/03

CPC classification number: H04L25/03885

Abstract: A continuous time linear equalizer (CTLE) circuit is provided. The CTLE circuit can include a differential pair of first and second transistors, the first and second transistors having drains connected through first and second drain resistors to a drain-side supply voltage node, and sources connected together by a source resistor and connected to one or more current sources, the first transistor in the differential pair having a gate connected to a reference voltage, and the second transistor in the differential pair having a gate connected to an input voltage, the drains of the first and second transistors providing a differential pair of signals as an output voltage, a first coupling capacitor connected between the source of the first transistor and the input voltage, and a second coupling capacitor connected to the source of the second transistor.

公开(公告)号：US20250105789A1

公开(公告)日：2025-03-27

申请号：US18371217

申请日：2023-09-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shang-Chi YANG ,  Tung-Yu LI ,  Jian-Syu LIN

IPC: H03F1/02 ,  H03F3/45

Abstract: A differential amplifier includes an input pair of transistors with a source-side resistor circuit, having a transistor biased in a triode region, and a current source. The resistor circuit in combination with a capacitance, causes source degeneration in the amplifier. The source side resistor circuit includes a first MOS transistor having a first channel terminal connected to the source of a first transistor in the differential pair, and a second channel terminal connected to the bulk terminal, and a second MOS transistor having a first channel terminal connected to the source of a second transistor in the differential pair, and a second channel terminal connected to the bulk terminal. A bias circuit biases the first MOS transistor and the second MOS transistor in a triode region. The resistance of the source-side resistor circuit and the gain of the transistors in the differential amplifier can track across process corners.