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    METHOD AND SYSTEM FOR ENHANCED READ PERFORMANCE IN LOW PIN COUNT INTERFACE
    3.
    发明申请
    METHOD AND SYSTEM FOR ENHANCED READ PERFORMANCE IN LOW PIN COUNT INTERFACE 有权

    公开(公告)号：US20210280222A1

    公开(公告)日：2021-09-09

    申请号：US17070340

    申请日：2020-10-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long CHANG ,  Su-Chueh LO ,  Yung-Feng LIN

    IPC: G11C7/10 ,  G11C7/22 ,  G06F9/38 ,  G06F9/445

    Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

    MEMORY DEVICE AND OPERATION METHOD THEREOF
    4.
    发明申请
    MEMORY DEVICE AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20220375523A1

    公开(公告)日：2022-11-24

    申请号：US17325243

    申请日：2021-05-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yung-Feng LIN ,  Su-Chueh LO ,  Teng-Hao YEH ,  Hang-Ting LUE

    IPC: G11C16/08 ,  G11C16/24 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

    Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.

    VOLTAGE REGULATOR WITH IMPROVED SLEW RATE
    5.
    发明申请
    VOLTAGE REGULATOR WITH IMPROVED SLEW RATE 审中-公开

    公开(公告)号：US20190050012A1

    公开(公告)日：2019-02-14

    申请号：US15673644

    申请日：2017-08-10

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shang-Chi YANG ,  Su-Chueh LO

    IPC: G05F1/575

    Abstract: A voltage regulator supplies a regulated voltage on an output node. The voltage regulator includes a two stage amplifier which controls an output leg including the output node, and a feedback circuit between the output node and an input of the amplifier. The first stage is connected to a first power supply circuit configured to be connected to a first power supply, such as a charge pump. The second stage is connected to a second power supply circuit configured to connect to a second power supply, such as an external power supply. The first power supply and second power supply are different. The second stage is turned off during a transition in current loading, before the first stage, so that final control of the regulated voltage can be achieved using the first stage, and the slew rate is boosted using the second stage.

    WRITE-WHILE-READ ACCESS METHOD FOR A MEMORY DEVICE
    7.
    发明申请
    WRITE-WHILE-READ ACCESS METHOD FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：US20180335980A1

    公开(公告)日：2018-11-22

    申请号：US15890595

    申请日：2018-02-07

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long CHANG ,  Ken-Hui CHEN ,  Su-Chueh LO ,  Shang-Chi YANG

    IPC: G06F3/06

    Abstract: A memory device includes a memory including first and second pages in first and second banks, respectively, an address decoder mapping command addresses to physical addresses. The memory device further includes circuitry configured to maintain a status indicating a most recently written page, decode received command sequences including command addresses and implementing an operation including (i) responsive to receiving a command sequence including a read command address that is pre-configured for reading data, causing the address decoder to map the read command address to one of the first and second pages selected according to the status, and (ii) responsive to receiving a second command sequence including a write command address that is pre-configured for writing data, causing the address decoder to map the write command address to one of the first and second pages selected according to the status.

    BOND PAD LAYOUT INCLUDING FLOATING CONDUCTIVE SECTIONS
    9.
    发明申请
    BOND PAD LAYOUT INCLUDING FLOATING CONDUCTIVE SECTIONS 有权

    公开(公告)号：US20230056520A1

    公开(公告)日：2023-02-23

    申请号：US17405812

    申请日：2021-08-18

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Su-Chueh LO ,  Jian-Syu LIN ,  Yi-Fan CHANG

    IPC: H01L23/00

    Abstract: Disclosed is a semiconductor device that has a first layer including conductive material, a bond wire coupled to an upper surface of the first layer, and a second layer including conductive material underneath the first layer. One or more interconnects couple the second layer to the first layer. In an example, the second layer has a plurality of discontinuous sections that includes (i) a connected section coupled to the one or more interconnects and (ii) one or more floating sections that are at least in part surrounded by the connected section, where the one or more floating sections are electrically floating and isolated from the connected section. The semiconductor device also includes an under-pad circuit on a substrate underneath the second layer, the under-pad circuit to transmit signals to one or more components external to the semiconductor device though the first layer.

    MEMORY APPARATUS AND ASSOCIATED CONTROL METHOD FOR REDUCING ERASE DISTURB OF NON-VOLATILE MEMORY
    10.
    发明申请
    MEMORY APPARATUS AND ASSOCIATED CONTROL METHOD FOR REDUCING ERASE DISTURB OF NON-VOLATILE MEMORY 有权

    公开(公告)号：US20210366557A1

    公开(公告)日：2021-11-25

    申请号：US17178313

    申请日：2021-02-18

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Su-Chueh LO ,  Kuen-Long CHANG

    IPC: G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C16/30

    Abstract: A memory apparatus and a control method are provided. The memory apparatus includes a non-volatile memory array having plural memory groups, and the control method is applied to the non-volatile memory array. The memory groups jointly share a first well, and the control method is applied to the non-volatile memory array. A first memory group among the memory groups is erased according to a first erase command after the memory apparatus is power-on, and a first amount of the memory groups are recovered in a first erase-recover procedure after the first memory group is erased. A second memory group among the memory groups is erased according to a second erase command after the first erase-recover procedure, and a second amount of the memory groups are recovered in a second erase-recover procedure after the second memory group is erased. The first amount is greater than the second amount.

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