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公开(公告)号:US11587617B2
公开(公告)日:2023-02-21
申请号:US17333046
申请日:2021-05-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor: Po-Hao Tseng , Feng-Min Lee , Ming-Hsiu Lee , Liang-Yu Chen , Yun-Yuan Wang
IPC: G11C15/04 , G11C11/404 , G11C16/04 , G11C15/00
Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.
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公开(公告)号:US11521973B2
公开(公告)日:2022-12-06
申请号:US16936544
申请日:2020-07-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor: Liang-Yu Chen
IPC: G11C15/04 , H01L27/10 , H01L27/105 , H01L27/02
Abstract: Disclosed is a 3D architecture of ternary content-addressable memory (TCAM), comprising a first transistor layer, a second transistor layer, a third transistor layer and a fourth transistor layer. The first transistor layer and the second transistor layer are disposed on a first plane. The third transistor layer and the fourth transistor layer are respectively stacked on the first transistor layer and the second transistor layer in a second direction perpendicular to the first plane. Two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a first memory cell of the TCAM. The other two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a second memory cell of the TCAM.
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