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公开(公告)号：US20240412784A1
公开(公告)日：2024-12-12
申请号：US18330369
申请日：2023-06-07
Applicant: MACRONIX International Co., Ltd.
Inventor： Yu-Yu Lin , Feng-Min Lee
IPC: G11C13/00
Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.
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公开(公告)号：US12159673B2
公开(公告)日：2024-12-03
申请号：US18354706
申请日：2023-07-19
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Feng-Min Lee , Ming-Hsiu Lee
Abstract: A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.
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公开(公告)号：US12159671B2
公开(公告)日：2024-12-03
申请号：US18164657
申请日：2023-02-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Feng-Min Lee , Yu-Hsuan Lin
IPC: G11C15/04
Abstract: An in-dynamic memory search device and an operation method thereof are provided. The in-dynamic memory search device includes at least one word line, at least two bit lines, at least one match line, at least one unit cell, at least two search lines, at least one pre-charge unit and at least one sense unit. The unit cell includes two storage elements and two search transistors. Each of the storage elements includes a write transistor and a read transistor. The write transistor is connected to the word line and one of the bit lines. The read transistor is connected to the write transistor and the match line. The search transistors are respectively connected to the read transistors. The search lines are respectively connected to the search transistors. The pre-charge unit is connected to the match line. The sense unit is connected to the match line.
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公开(公告)号：US20240304238A1
公开(公告)日：2024-09-12
申请号：US18180145
申请日：2023-03-08
Applicant: MACRONIX International Co., Ltd.
Inventor： Feng-Min Lee , Yu-Yu Lin
IPC: G11C11/4096 , G11C11/4093
CPC classification number: G11C11/4096 , G11C11/4093
Abstract: The disclosure provides a cache device, which includes: a first transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the first transistor is coupled to an input voltage, and the second terminal of the first transistor is coupled to a storage node; an inverter having an input terminal and an output terminal, in which the input terminal is coupled to the storage node; and a second transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the second transistor is coupled to the output terminal of the inverter, and the second terminal of the second transistor is configured to output a read voltage.
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公开(公告)号：US11823749B2
公开(公告)日：2023-11-21
申请号：US17471193
申请日：2021-09-10
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Feng-Min Lee , Ming-Hsiu Lee
CPC classification number: G11C16/3404 , G11C15/04 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/30
Abstract: The application provides a Content Addressable Memory (CAM) cell, a CAM memory device and an operation method thereof. The CAM cell includes: a plurality of parallel-coupled flash memory cells: wherein a storage data of the CAM cell is based on a combination of a plurality of threshold voltages of the parallel-coupled flash memory cells.
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Patent Agency Ranking
公开(公告)号：US11562229B2
公开(公告)日：2023-01-24
申请号：US16450334
申请日：2019-06-24
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee
Abstract: A method for accelerating a convolution of a kernel matrix over an input matrix for computation of an output matrix using in-memory computation involves storing in different sets of cells, in an array of cells, respective combinations of elements of the kernel matrix or of multiple kernel matrices. To perform the convolution, a sequence of input vectors from an input matrix is applied to the array. Each of the input vectors is applied to the different sets of cells in parallel for computation during the same time interval. The outputs from each of the different sets of cells generated in response to each input vector are sensed to produce a set of data representing the contributions of that input vector to multiple elements of an output matrix. The sets of data generated across the input matrix are used to produce the output matrix.
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公开(公告)号：US11062197B2
公开(公告)日：2021-07-13
申请号：US15803971
申请日：2017-11-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee
Abstract: A neuromorphic computing system includes a synapse array, a switching circuit, a sensing circuit and a processing circuit. The synapse array includes row lines, column lines and synapses. The processing circuit is coupled to the switching circuit and the sensing circuit and is configured to connect a particular column line in the column lines to the first terminal by using the switching circuit, obtain a first voltage value from the particular column line by using the sensing circuit when the particular line is connected to the first terminal, connect the particular column line to the second terminal by using the switching circuit, obtain a second voltage value from the particular column line by using the sensing circuit when the particular line is connected to the second terminal, and estimate a sum-of-product sensing value according to a voltage difference between the first voltage value and the second voltage value.
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公开(公告)号：US10528862B1
公开(公告)日：2020-01-07
申请号：US16222222
申请日：2018-12-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee
IPC: G11C16/04 , G06N3/02 , G11C16/08 , H01L29/788 , G11C16/26 , H01L27/11524 , G11C16/10
Abstract: A neural network system includes a doping well having a first conductivity, a memory string having a plurality of memory cells each include a gate and a source/drain with a second conductivity disposed in the doping well, a buried channel layer having the second conductivity and disposed in the doping well, a word line driver used to apply input voltages corresponding to a plurality of input variations of terms in the sum-of-products operations, a voltage sensing circuit used to apply a constant current into the memory string and to sensing a voltage, a controller used to program/read the memory cells for acquiring a plurality of threshold voltages corresponds to weights of the terms in the sum-of-products operations. When programing/reading the threshold voltages, a first bias voltage is applied to the first doping well; and when sensing the voltage, a second bias voltage is applied to the first doping well.
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公开(公告)号：US10157963B1
公开(公告)日：2018-12-18
申请号：US15712474
申请日：2017-09-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Dai-Ying Lee , Erh-Kun Lai , Feng-Min Lee
Abstract: A semiconductor device includes a substrate and a memory structure disposed above the substrate. An embodied memory structure includes a bottom electrode disposed above the substrate, a barrier layer disposed at the bottom electrode, a resistance switching layer disposed on the bottom electrode and above the barrier layer, and a top electrode disposed on the resistance switching layer and covering the resistance switching layer. A bottom surface of the resistance switching layer is spaced apart from an uppermost surface of the barrier layer by a distance.
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10.发明授权公开(公告)号：US10103895B1
公开(公告)日：2018-10-16
申请号：US15782890
申请日：2017-10-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Yu-Yu Lin , Kai-Chieh Hsu , Feng-Min Lee
Abstract: A method for physically unclonable function-identification (PUF-ID) generation includes: providing a PUF array having programmable resistance memory cells; performing a forming procedure followed by a programming procedure on all of the programmable resistance memory cells of the PUF array; performing an estimation process to estimate randomness of the PUF array, by comparing a reference current of a base unit to a total current passing through all of the programmable resistance memory cells for obtaining a PUF randomness; determining a setting result of randomness based on the estimation process; and generating a PUF-ID according to the setting result of randomness.
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